Charge trapping related degradation of thin HfAlO/SiO2 gate dielectric stack during constant-voltage stress

Article abstract of DOI:10.1149/1.3148203

Charge carrier generation/trapping and the related degradation of a thin HfAlO/SiO₂ stack in n-type metal-oxide-semiconductor capacitors have been investigated under constant gate voltage stress. The results show that dielectric degradation is

Full text of DOI:10.1149/1.3148203

Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
H661
0
013-4651/2009/156͑8͒/H661/8/$25.00 © The Electrochemical Society
Charge Trapping Related Degradation of Thin HfAlOÕSiO2
Gate Dielectric Stack during Constant-Voltage Stress
a,z
b, ,z
c
Piyas Samanta, Chin-Lung Cheng, * and Yao-Jen Lee
a
Department of Physics, Vidyasagar College for Women, Kolkata 700 006, India
b
Institute of Mechanical and Electro-Mechanical Engineering, National Formosa University, Yunlin 63201,
Taiwan
c
National Nano Device Laboratories, Hsinchu 30078, Taiwan
Charge carrier generation/trapping and the related degradation of a thin HfAlO/SiO stack in n-type metal-oxide-semiconductor
2
capacitors have been investigated under constant gate voltage stress. The results show that dielectric degradation is a composite
effect of neutral trap creation, surface state generation at the Si/SiO interface, and positive charge trapping in the bulk. The
2
neutral traps created during stress are homogeneously distributed across the oxide following Poisson’s random statistics. A
significant amount of border-trapped charges was observed in both as-deposited and poststressed devices. The kinetics of genera-
tion of both oxide-trapped positive charges and interface trapped charges are found to be similar. Both these defects are possibly
created by the hydrogen-related species. We demonstrate that compared to HfO devices, HfAlO devices with an equal equivalent
2
oxide thickness ͑EOT͒ show better performances in memory and logic applications. On the contrary, at a given stress voltage, the
threshold voltage degradation ⌬VT and stress-induced leakage current degradation in HfAlO samples are larger, indicating a
shorter device lifetime compared to the HfO samples of the same EOT.
2
©
2009 The Electrochemical Society. ͓DOI: 10.1149/1.3148203͔ All rights reserved.
Manuscript submitted March 23, 2009; revised manuscript received May 8, 2009. Published June 18, 2009.
Scaling down the conventional silicon dioxide ͑SiO ͒ film thick-
ness below ϳ2 nm in complementary metal oxide semiconductor
CMOS͒ devices leads to excessive leakage current due to the direct
tunneling of electrons between the electrodes and device reliability
problems. To provide sufficient gate control with reduced gate leak-
age current, alternative high-␬ dielectrics having a permittivity
30 s and back side aluminum deposition for ohmic contact. Several
identical test capacitors with gate areas of 150 ϫ 150, 100 ϫ 100,
and 50 ϫ 50 ␮m were used in this study. Devices were subjected to
dc CVS under negative bias on the TaN gate, keeping the p-type Si
in accumulation. Stressing and sensing measurements were done on
several identical test structures at room temperature in a dark-
shielded chamber using a Keithley 4200 semiconductor character-
ization system ͑SCS͒ and Keithley 236 source measure units.
Capacitance–voltage ͑C-V͒ measurements were done using an Agi-
lent 4284A precision LCR meter controlled by SCS via a Keithley
708A switching matrix.
2
͑
higher than SiO are being extensively investigated for future gen-
2
1-17
eration CMOS devices.
Among the various high-␬ dielectrics
being studied, hafnium oxide ͑HfO ͒ has emerged as the most prom-
2
ising candidate due to its relatively high dielectric constant
͑
ϳ 22͒, large bandgap ͑ ϳ 5.25 eV͒, large conduction- and
valence-band offsets, and compatibility with the polysilicon gate
The flatband voltage ͑VFB͒, midgap voltage ͑Vmg͒, and the chan-
nel threshold voltage ͑VT͒ were estimated utilizing the measured
high frequency ͑100 kHz͒ C-V data ͑swept from inversion to accu-
mulation͒ and theoretical simulation incorporating the quantum me-
chanical ͑QM͒ effect including the wave function penetration in
2
,7,17
process.
However, the major drawback of HfO is that pure
2
6,7
as-deposited amorphous HfO crystallizes at 400–450°C, result-
2
ing in a large leakage current and the paths for oxygen or dopant
diffusion in the dielectric via grain boundaries, threshold voltage
7,8
6
18
instability, and defect generation. Recently, Zhu et al. showed
SiO2. From QM simulation, the extracted equivalent oxide thick-
that alloying of HfO and Al O increases the crystallization tem-
ness ͑EOT͒ of the stack was Ϸ2.63 nm ͑within 5% variation in
several devices͒. The capacitance equivalent thickness extracted
from the measured capacitance in accumulation was Ϸ2.83 nm. The
calculated dielectric constant of the deposited HfAlO was about
12.4.
2
2
3
perature up to 1000°C compatible with the thermal budget in stan-
dard CMOS process. In the past few years, considerable progress
has been made in understanding the effect of aluminum inclusion on
electrical and material properties of hafnium aluminate ͑HfAlO͒
6
-10
11,12
films.
However, little work
has been done in assessing the
reliability of HfAlO films with a tantalum nitride ͑TaN͒ gate. We
therefore attempt to investigate charge-carrier generation/trapping in
HfAlO dielectrics during constant voltage stress ͑CVS͒ to gain bet-
ter physical insights into the generation mechanism of oxide
charges.
Results and Discussion
Device characterization.— The measured C-V characteristics
with as-deposited HfAlO films exhibit a good saturation behavior in
accumulation of p-Si at the ac signal frequencies in the range be-
tween 1 and 200 kHz, as shown in Fig. 1a. In Fig. 1a the frequency
dispersion in the effective dielectric constant of the HfAlO stack
was insignificant, indicating a low series resistance associated with
the device structure. This is further supported by the identical values
of the capacitances measured in the accumulation regime in both
series and parallel mode at a given bias and frequency, as depicted in
Fig. 1b. Therefore, hereafter in assessing the dielectric quality dur-
ing stress, the C-V curves were measured in parallel mode at an ac
signal frequency of 100 kHz. A low series resistance of the device
structure was achieved due to the ohmic contact of the back side of
the wafer. The energy band diagram of the nMOS capacitors with a
Experimental
Following the standard RCA cleaning process, ͑100͒-oriented
boron-doped p-type Si wafer of 15–25 ⍀ cm resistivity was ther-
mally oxidized in dry oxygen at 800°C to form an interfacial SiO2
2
nm thick as measured by spectroscopic ellipsometry. A 2 nm thick
HfAlO film was deposited on the SiO2 layer using atomic layer
deposition from a HfO –Al O combination with a 1:1 weight ratio.
2
2
3
After formation of the gate stack, a 100 nm thick TaN metal gate
was deposited by reactive sputtering on top of the high-␬ layer. All
n-type metal-oxide-semiconductor ͑nMOS͒ capacitors received
HfAlO/SiO stack is shown in Fig. 2a taking the work function of
2
1
2
postmetallization rapid thermal annealing at 750°C in N gas for
TaN on HfAlO as 4.5 eV. The important energy parameters, viz.,
conduction- and valence-band offsets, bandgap of HfAlO as de-
picted in Fig. 2a, were estimated according to the prescriptions by
2
1
7
Yu et al. and taking mole fraction of HfO in ͑HfO ͒ ͑Al O ͒
*
Electrochemical Society Active Member.
E-mail: piyasគsamanta@yahoo.com; chengcl@nfu.edu.tw
2
2 x
2
3 1−x
z
as 0.5.
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H662
Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
10-14 (b)
2
1
(
a)
HfAlO
1
10
1
0
EOT ~ 2.6 nm
30
20
10
0
30
20
10
0
Mode
00
TaN/HfAlO/SiO /p-Si
-1
2
Cp-G
10
10
10
10
10
1
1
1
1
EOT = 2.64 nm
Area = 2.5x10 cm
-2
Cs-R
s
-5
2
-3
-4
-5
f = 100 kHz
TaN/HfAlO/SiO /p-Si
EOT = 2.64 nm
Area = 2.5x10 cm
10-15
1
1
1
2
kHz
2
0 kHz
00 kHz
00 kHz
-5
2
HfAlO
Area = 10 cm
-6
0
0
0
0
-4
2
-
7
8
Gate injection
Area = 10 cm
FN slope = 73 MV/cm
Fresh
PBD (1 Sweep)
PBD (2 Sweep)
-
-4
2
st
-9
nd
(a)
(b)
0-16
1
0
-2
-4
-6
-8
0.16 0.18 0.20 0.22 -10.24
-
4
-3 -2 -1
0
1
-4 -3 -2 -1
0
1
2
-1
Gate Bias (V)
|EHfAlO
| (MV/cm)
Gate Bias (V)
Gate Bias (V)
Figure 3. Absolute magnitude of gate tunneling current density Jg as a
function of ͑a͒ applied gate bias and ͑b͒ electric field across the HfAlO layer.
Figure 1. ͑a͒ A typical multifrequency capacitance–voltage ͑C-V͒ plot of an
nMOS capacitor with a HfAlO/SiO2 gate stack. ͑b͒ C-V plot of a HfAlO
MOS capacitor in series and parallel modes at an ac signal frequency of
1
00 kHz. All measurements were recorded by sweeping the gate bias from
inversion to accumulation of the p-Si.
range studied here. The overlapping of the postbreakdown sweep
J-V characteristics in Fig. 3a indicates hard breakdown. At an elec-
tric field Ehk above 4 MV/cm in the HfAlO layer and before dielec-
tric breakdown, the current through the HfAlO layer is due to
From the full QM simulation of the measured C-V results, the
estimated VFB of the as-fabricated capacitors was Ϸ+0.19 V. The
1
9
Fowler–Nordheim ͑FN͒ tunneling, as seen from the straight-line fit
positive VFB caused due to incorporation of Al into HfO was also
2
7,9
2
reported by several researchers. Considering the work function
difference between the p-type Si substrate and TaN metal gate, VFB
should be about −0.25 V. Consequently, negative fixed charges
to ln͑Jg/Ehk͒ vs 1/Ehk plot of the measurement results illustrated in
Fig. 3b. The FN slope during gate injection in as-fabricated HfAlO
devices was 73 MV/cm as estimated from numerical fit of the mea-
1
9
were present in the HfAlO/SiO stack and its density was estimated
sured data with the well-known FN equation given by
2
to be about 3.5 ϫ 1012 cm . As-fabricated HfAlO capacitors ex-
hibit a significant hysteresis during double-bias sweep measurement,
as depicted in Fig. 2b. About 138 mV of negative VFB shift was
observed after the second sweep, i.e., when going back to inversion
from accumulation, as illustrated in Fig. 2b. We believe that the C-V
hysteresis in the metal-oxide-semiconductor ͑MOS͒ capacitor is at-
tributed to electron charging and discharging by direct tunneling
−2
2
hk
JFN = AFN
E
exp͑− BFN/Ehk͒
͓1͔
where AFN and BFN are constants and Ehk is the electric field across
the HfAlO layer as calculated from
Vhk
Vdi
Ehk =
=
͓2a͔
͓2b͔
Thk
␧
hk
through the ultrathin SiO to the substrate. From the above value of
2
Thk
+
ͩ ͪTox
VFB shift, the effective density of detrapped electrons was found to
␧ox
12
−2
be about 1.1 ϫ 10 cm .
Figure 3a shows the tunneling current density J as a function of
Vdi = V − V − ␺
g FB Si
g
applied gate bias keeping p-Si in accumulation. Multiple break-
downs were not observed in the HfAlO devices up to the voltage
where Vhk is the voltage drop in the high-␬ layer, Tox and Thk are the
physical thicknesses of SiO ͑permittivity ␧ ͒ and high-␬ dielectric
2
ox
͑
permittivity ␧ ͒, respectively, and V is the voltage drop across the
hk di
dielectric stack. V , VFB, and ␺ are the gate voltage, flatband volt-
age, and surface potential in silicon, respectively.
Evac
g
Si
χ= 2.5 eV
χ= 0.9 eV
1
20
To study the wafer level reliability, we have performed the
ramped voltage stress ͑RVS͒ measurement with a step size of 0.03 V
corresponding to a linear voltage ramp rate of about 0.75 MV/cm s
in several identical capacitors of various gate areas. The statistics of
dielectric breakdown voltage VBD obeys the Weibull distribution
given by
Φm
=
φ = 3.15 eV
E =
4
.5 eV
100
80
∆
C
φ = 2.0 eV
2.14 eV
Eg= 1.12 eV
Eg
=
Eg=
5
.885 eV 9.0 eV
EF
TaN
∆EV =
60
2
.625 eV
HfAlO
␤
V
BD
4
2
0
0
0
HfAlO
Area = 10 cm
f = 100 kHz
F͑VBD͒ = 1 − exp
ͭ
−
ͩ ͪ
ͮ
͓3͔
SiO2
p-Si
-4
2
␣
where F is the cumulative failure probability, V is the random
variable for breakdown voltage, ␣ is the breakdown voltage at the
failure percentage of 63.2%, and ␤ is the shape factor or Weibull
δV = 138 mV
BD
fb
(
a)
-
4
-3 -2 -1
0
1
2
slope. In Fig. 4a, the time-zero dielectric breakdown voltage ͑VBD
͒
(b)
Gate Bias (V)
distributions are shown for various capacitor sizes. The gate volt-
ages to breakdown Vg,BD were taken from the sweep I-V character-
istics during RVS. Using Eq. 2b, VBD was estimated from the mea-
sured values of Vg,BD, VFB, and ␾Si of each individual capacitor. If
the breakdown distributions follow Poisson’s random statistics, we
Figure 2. ͑a͒ Schematic energy band diagram of nMOS capacitor with
HfAlO/SiO stack. ͑b͒ Bidirectional HFCV characteristics of a virgin nMOS
2
capacitor with a HfAlO/SiO stack dielectric. Data were recorded from in-
2
version to accumulation ͑solid circles͒ and back to inversion ͑open circles͒.
2
0
Solid lines are from QM simulation.
have
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Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
H663
Area
Area
2.25x10 cm
2
0
2
4
120 (a)
0
-100
-200
-300
(b)
TaN/HfAlO/SiO /p-Si
TaN/HfAlO/SiO /p-Si
-
4
2
2
2
2
2
2
1
2
.25x10 cm
-4
2
-4
-4
Area = 10 cm
Area = 10 cm
2
0
2
4
-
4
2
2
.0x10 cm
.5x10 cm
-4
2
2
100
1.0x10 cm
-
5
-5
Fresh
Post CVS
@ -3.8 V
for 100 s
for 1000 s
simulation
2.5x10 cm
8
0
HfAlO
EOT~2.6 nm
VBD = -5.42 V
-
-
60
4
0
-
-
-
400
500
HfAlO
EOT~2.6 nm
20
0
CVS@ -3.8 V
CVS@ -4.2 V
(a)
6 2
(
b)
-
-6
4
5
4
6
-2
-1
0
1
2
01
102
103
1
-
VBD (V)
-VBD (V)
Gate Bias (V)
Stress Time (s)
Figure 5. ͑a͒ HFCV characteristics of an nMOS capacitor with
a
Figure 4. ͑a͒ Individual Weibull distributions of breakdown voltage VBD of
HfAlO capacitors for different areas. ͑b͒ Normalized Weibull plot of VBD
with the identical data from ͑a͒ by using Eq. 4 at a reference area of 2.5
ϫ 10 cm . Line is the fit to Weibull statistics. The dielectric breakdown
voltage at 63.2% of failure percentile was estimated at 5.42 V.
HfAlO/SiO stack dielectric measured before and after CVS at −3.8 V for
2
16
different times. Solid lines are from QM simulation. ͑b͒ Stress time depen-
dence of midgap voltage shift during CVS with stress voltage Vg
stress
−
5
2
as a
parameter. Solid lines are from power-law fit.
as-fabricated devices was ͑2–3͒ ϫ 1010 cm−2 eV . The instanta-
−1
S
1
neous value of Dit was calculated from the single high frequency
ln͕− ln͓1 − F͑VBD1͔͖͒ − ln͕− ln͓1 − F͑VBD2͔͖͒ = lnͩ ͪ ͓4͔
23
S
͑100 kHz͒ C-V and G-V data according to
2
2
2 −1
where VBD1 and VBD2 are the dielectric voltages to breakdown for
capacitors with areas S and S , respectively. Figure 4b shows area-
scaled Weibull W ϵ ln͓−ln͑1 − F͔͒, where the individual VBD dis-
tributions for different gate areas are normalized to 2.5
ϫ 10 cm using Eq. 4. In Fig. 4b the normalized V distributions
of various capacitor areas merge to a single Weibull breakdown
distribution, indicating that the defect-related dielectric breakdown
is intrinsic and can be explained by the precolation model. Fur-
thermore, the overlap of the area-scaled Weibulls of capacitors of
various sizes, as shown in Fig. 4b, reveals that the defects in the
dielectric are homogeneously distributed across the oxide area fol-
lowing Poisson random statistics. From the merged Weibull distri-
bution of VBD, the estimated dielectric breakdown voltage at 63.2%
failure percentile was −5.42 V which corresponds to 20.6 and
2͑G
/␻͒
G
Cm
m,max
m,max
D = ͭ ͮ
ͫ
ͩ ͪ
+
ͩ
1 −
ͪ
ͬ
͓6͔
it
1
2
qS
␻C
Cox
ox
where Gm,max is the maximum ac conductance with its correspond-
ing capacitance C , C is the oxide capacitance as measured from
the QM simulation, and S and ␻ are the capacitor area and ac
−
5
2
m
ox
BD
18
20
signal frequency in rad/s, respectively. Figure 7b shows the variation
2
1
in the density of stress-induced interface states ⌬D at various val-
it
stress
ues of Vg . Similar to the oxide-trapped positive charges, interface
stress
state generation is accelerated with increasing Vg , which in turn
is related to the electron energy reaching the anode.
20
SILC.— The gate current density at a given sensing gate voltage
sense
g
V
increases after CVS. This increase ⌬J in gate current from its
g
prestress value Jg0 is called the stress-induced leakage current
SILC͒ and is often described by the “normalized SILC” defined as
J /J . Figure 8a is a typical plot showing the normalized SILC
6
.5 MV/cm of the electric fields across the interfacial SiO2 and
͑
⌬
HfAlO layers, respectively.
g
g0
Charge carrier trapping.— To study the stress-induced charge
generation/trapping in the gate stack, high frequency capacitance–
voltage ͑HFCV͒ measurements were performed before and after
CVS. In our devices, HFCV curves shifted toward more negative
voltage after CVS, as depicted in Fig. 5a, indicating positive charge
5
HfAlO
Area = 2.25x10 cm
EOT = 2.63 nm
CVS@ -3.75 V
CVS@ -4.0 V ξ
-4
2
2
2
buildup in the gate dielectric. Positive oxide charge trapping was
further confirmed ͑Fig. 5b͒ from the negative shift ⌬Vmg of the
midgap voltage after electrical stress relative to the fresh device
4
3
2
1
0
A[1-Exp{-(t/ ) }]
0.2
A[1-Exp(-t/ )] + Bt
2,14
following the relationship
A[1-Exp(-t/ )]
⌬
Vmg␧ox
⌬
Not = −
͓5͔
qTeq
where q is the magnitude of electronic charge, Teq is the EOT of the
gate stack, and ⌬Not is the variation in the density of stress-induced
oxide-trapped charges. The variations in the density of stress-
induced oxide-trapped positive charges ⌬N+ are shown in Fig. 6 as
ot
a function of stress time during CVS at various stress voltages. C-V
02
103
104
1
measurement is sensitive to the charges trapped closer to the Si/SiO
2
2
2
interface. Consequently, the positive oxide charge is located close
Stress Time (s)
13
to the Si/SiO interface.
2
The change in the conductance peak value after CVS relative to
Figure 6. Variation in the density of oxide-trapped positive charges ⌬N+
with stress time during CVS at different voltages. Symbols are from experi-
ment. Curves are fits to various theoretical models.
ot
the virgin device shown in Fig. 7a indicates interface state D gen-
it
22
eration during stress. Estimated midgap surface state density D in
it
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H664
Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
1
0-5
0-6
0-7
60 (a)
50
HfAlO
Area = 2.25x10 cm
EOT = 2.6 nm
(b)
TaN/HfAlO/SiO /p-Si
TaN/HfAlO/SiO /p-Si
2
2
0.20
-4
2
TaN/HfAlO/SiO /p-Si
-
4
2
2
-4
EOT = 2.63 nm
Area = 2.25x10 cm
2
Area = 2.25x10-4 cm2
Area = 2.25x10 cm
EOT = 2.6 nm
EOT = 2.63 nm
CVS@ -3.5 V
CVS@ -3.8 V
CVS@ -4.25 V
0
0
0
.15
.10
.05
stress
Vg
= -4.0 V
10-3
1
1
1
40
0.2
~t
3
0
stress
Vg
= -3.75 V
20
10
0
Fresh
Experiment
Post CVS@ -4.0 V
for 5000 s
stress
2
a(|V
|/Eth-1)
g
f = 100 kHz
stress
Eth = 2.2 eV
Vg
= -3.5 V
10-4
(
a)
(b)
0-
8
0.00
1
01
10
2
10
3
104
-
0.50 -0.25 0.00 0.25 0.50
0
100 200 300 400
Stress Time (s)
3.0 3.5 4.0 4.5 5.0
Stress Time (s)
Gate Bias (V)
stress
-Vg
(V)
Figure 7. ͑a͒ High frequency conductance–voltage characteristics ͑parallel
Figure 9. ͑a͒ Stress time dependence of the increase in absolute magnitude
of tunneling current density Jg relative to the fresh device observed during
CVS with stress voltage as a parameter. Solid and dashed lines are fits to Eq.
mode͒ of an nMOS capacitor with a HfAlO/SiO stack dielectric measured
2
before and after CVS at −4.0 V for 5000 s. ͑b͒ Variation in the density of
surface states ⌬Dit with stress time during CVS at different voltages. Sym-
bols are from experiment. Curves are from power-law fits.
7
and the first term on right side of Eq. 7, respectively. ͑b͒ Normalized trap
generation rate per injected electron as a function of stress voltage in a MOS
capacitor with a HfAlO/SiO stack. Solid line is fit to Eq. 8.
2
spectra measured immediately after CVS at −4.0 V for different
times. The normalized SILC spectra show two distinct peaks at
propose that stress-induced interface traps do not play a role in the
sense
V
= −2.175 and −2.625 V, indicating two distinct conducting
g
24
SILC observed beyond VFB through the HfAlO stack deposited on
paths. To explain the SILC conduction mechanism, Ghetti et al.
24
nondegenerately doped Si, contrary to the article dealing in de-
proposed trap-assisted tunneling ͑TAT͒ via surface states in control
oxide devices. However, although a significant amount of interface
states is generated during CVS, TAT via surface states cannot ex-
plain the observed SILC in our HfAlO devices as explained below.
vices on heavily doped Si.
Stress-induced neutral trap creation in our devices is evident
from the nonsaturating behavior of the time evolution of J during
g
CVS for different stress voltages, as depicted in Fig. 9a. The non-
First, TAT via D to be the conduction mechanism of SILC, normal-
it
saturating behavior of J was also observed at a longer stress time
sense
g
ized SILC at a given Vg , should exhibit a proportionality to the
surface state density D as proposed by Ghetti et al. However, no
up to 10,000 s. This increase in J could be due to the enhanced
2
4
g
it
electric field at the cathode ͑TaN gate͒ due to the trapped positive
proportionality between either of the two peak values in the normal-
25
oxide charge and/or due to the TAT. Therefore, the increment
ized SILC spectrum and D is observed in our devices, as demon-
3,5
it
⌬
J ͑t͒ in J during CVS can be modeled by
g g
strated in Fig. 8b. Second, stress-induced interface traps are the
4
trivalent Si w Si* dangling bonds, so-called P centers exhibit-
t
3
b0
␦
22
⌬J = A 1 − exp
ͩ
−
ͪ
+ Bt
͓7͔
g
ͫ
ͬ
ing U-shaped distribution in the 1.12 eV bandgap of Si. Therefore,
for TAT via interface states to be a possible mechanism of SILC, the
normalized SILC spectrum should exhibit several peaks contrary to
the observed two peaks shown in Fig. 8a. In view of the above, we
␶
where A and ␶ are constants, ␦ is a fraction depending on the charge
state and atomicity of hydrogen during transport, and B is the trap
generation rate during CVS and is a function of electronic energy.
The first term on the right side of Eq. 7 takes into account the effect
of oxide charge buildup, while the second term takes care of the
SILC contribution via TAT. The first term alone cannot explain the
Vgstress = -4.0 V
HfAlO
6
5
4
3
2
1
0
st
1
2
~
SILC Peak
SILC Peak
3
2
nd
3
2
1
0
observed ⌬J − t variations in either of the devices, as evident from
g
t0.3
1
000 s
EOT = 2.63 nm
the dashed lines in Fig. 9a. Therefore, the increase in Jg is less
∆
D /D
it it0
.2
sensitive to the positive charge buildup in the dielectric. Rather, the
0
0.3
~t
time evolution ͑t dependence͒ of J during CVS can be best ex-
g
500 s
plained by the composite effects of the above two mechanisms
͑solid lines͒, as illustrated in Fig. 9a. Neutral electron trap creation
rate per injected electron in HfAlO capacitors is also shown in Fig.
9
b as a function of absolute magnitude of applied gate voltage dur-
100 s
ing CVS. The normalized value of the trap creation rate is
Bt
voltage is interrupted and Q is the injected electron flux during
the electrical stress. Evidently trap creation rate dN /dt follows
t
␦
CVS@ -4.0 V
/Q , where t
inj
is the total stress time at which the gate
stress
1
stress
3
HfAlO
inj
(
b)
EOT = 2.63 nm
5
(
a)
1
01
10
2
10
3
104
stress
2
-
1.6 -2.0 -2.4 -2.8
dNt
dt
͉Vg
͉
sense
Stress Time (s)
= C
ͩ
− 1
ͪ
͓8͔
Vg
(V)
Eth
where C is a constant and Eth is the threshold voltage for trap cre-
ation. The estimated value of Eth in HfAlO dielectric was found
Figure 8. ͑a͒ Normalized SILC measured after CVS at −4.0 V for different
times as a function of gate sensing voltage in an nMOS capacitor with
2
.2 eV.
HfAlO/SiO gate stack. ͑b͒ Plot of two peaks in the normalized SILC spec-
2
trum ͑open symbols͒ measured after CVS at −4.0 V ͑left y-axis͒ and gener-
ated surface state density normalized to its initial value Dit0 ͑filled symbols͒
Mechanism of charge carrier generation.— The origin of posi-
͑
right y-axis͒ as a function of injected electron fluence Qinj. Curves are from
tive oxide charge in a hafnium-based gate stack remains controver-
11,12,26,27 3-5
power-law fits.
sial between trapping of holes
and protons. The above
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Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
H665
TaN/HfAlO/SiO /p-Si
0.5
2
-4
HfAlO
EOT = 2.63 nm
-
-
-
450
425
400
2
Area = 2.25x10 cm
(EOT = 2.6 nm)
10-5
10-6
0.4
0.3
0.2
0.1
TaN/HfAlO/SiO /p-Si
2
-4
2
Area = 2.25x10 cm
stress
(
EOT = 2.6 nm)
Vg
@
+
12
-2
∆Not = 3.9 x10 cm
-3.75 V
4.0 V
during CVS@ -4.25 V
for 600 s
-
CVS@ -4.25 V for 600 s
a + b Ln( )
0
0
r
(
a)
(
b)
0-7
1
0.0
1016
1017
10
-2
18
1019
-
1
0
1
2
0
2
4
6
8
10
Ln(τ in hr)
Detrapping Time (hr)
r
Ninj (cm )
Figure 10. ͑a͒ Measured midgap voltage shift ⌬V* due to detrapping of
oxide positive charges at room temperature as a function of logarithmic time
␶r. Oxide positive charges were trapped at room temperature during CVS at
mg
Figure 11. Oxide positive charge trapping probability as a function of num-
ber of injected electrons into HfAlO/SiO stack during negative-bias CVS
2
with stress voltage as a parameter.
−
4.25 V for 600 s. ͑b͒ Density of detrapped oxide positive charge observed
at room temperature as a function of detrapping time ␶ . Zero-field emission
r
of oxide charge was measured ͑symbols͒ after CVS at −4.25 V for 600 s at
room temperature. Curve is from logarithmic fit.
ever, no such saturation in oxide positive charge buildup was ob-
served in either of the devices within the stress time shown in Fig. 6.
On the contrary, ⌬N+ monotonically increases with stress time, in-
ot
controversy is resolved in this section as follows. Zero-field detrap-
dicating generation of defects in the dielectric during stress. There-
fore, hole trapping via a VBT mechanism during negative-bias CVS
seems unlikely in these devices. To model the positive charge
buildup in high-␬ stacks due to hole trapping, the stretched-
ping of oxide-trapped positive charge is studied, as illustrated in Fig.
*
1
0. The straight-line nature of the midgap voltage shift ⌬V be-
mg
cause of self-detrapping vs logarithmic relaxation time ␶ , as shown
r
2
8
in Fig. 10a, indicates the existence of tunnel detrapping of bulk
positive oxide charges at room temperature. Tunnel detrapping of
proton-induced defects is not physically acceptable, rather it is con-
␨
exponential A͕1 − exp͓−͑t/␶͒ ͔͖ formalism has been made popular
26,27
+
ot
by several researchers.
Stress time dependence of ⌬N can be
mathematically well reproduced by the stretched exponential with
distribution width ␨ Ϸ 0.22, as shown by the filled dots in Fig. 6.
However, the stretched-exponential formulation ͑with ␤ Ͻ 1͒ is
14
formity with holes from as-fabricated traps. Therefore, hole trap-
ping might explain the oxide positive charge buildup in both de-
vices. A plot of the instantaneous zero-field emission rate of N+ vs
ot
based on the a priori assumption of continuous distribution of cap-
reciprocal of detrapping time ␶ yielded a straight line, as evident
26,27
r
ture cross section of the intrinsic hole traps
contrary to the single
from Fig. 10b. This means that intrinsic hole traps in the dielectric
time constant, as determined experimentally in Fig. 10b. Further-
2
8
stacks are uniformly distributed ͓D ͑E͒ = const͔ in energy in ac-
26
ox
more, the distributed capture cross-section model assumes only
cordance with
trap filling without creating additional traps. In view of the above,
2
6,27
+
the distributed capture cross-section model
is not physically vi-
dN
k TD ͑E͒
B ox
ot
=
͓9͔
able to explain the positive charge buildup during CVS in either of
the high-␬ gate stacks studied here.
dt
t
where N+ is the area density of detrapped positive oxide charge with
Hole trapping into as-fabricated hole traps of single capture cross
ot
3
1
−
2
−1
density of states D ͑E͒ in cm eV , k T is the thermal energy in
eV, and t is the detrapping or relaxation time. The constant density
section obeys the simple charging equation
p͑t͒ = A͓1
ox
B
− exp͑−t/␶͔͒. However, the estimated oxide positive charge density
+
of states suggests that the as-fabricated hole traps have a single time
⌬N in either of the devices does not fit with above hole-trapping
ot
2
8
+
ot
constant and therefore can be characterized by a single capture
cross section. Our analysis contradicts the observations by Gusev
dynamics, as depicted by the dashed lines in Fig. 6. Rather, ⌬N ͑t͒
fits well ͑the solid lines in Fig. 6͒ with
2
9
and D’Emic. We explain this in the following way. In their work,
the interfacial dielectric was ultrathin silicon oxynitride instead of
+
ot
n
⌬
N
= A͓1 − exp͑− t/␶͔͒ + Bt
͓10͔
thermal SiO used in our measurements and the interfacial dielectric
plays the role in positive charge and/or hole trapping. Using Eq. 9,
2
The first term on the right side of Eq. 10 is due to hole trapping in
pre-existing neutral traps via AHI, while the second term is due to
defect generation. The power-law exponent n Ϸ 0.2 in Eq. 10 repro-
the estimated depth of the intrinsic hole traps from the SiO valence
2
duces ⌬N+ during CVS, as depicted in Fig. 6. ␦ Ϸ 0.2 is consistent
bandedge was Ϸ1.2 eV. This value is close to that reported for
28
ot
intrinsic hole traps in pure SiO devices.
2
with the dispersive transport of proton through the interfacial SiO
2
3
2
The origin of trapped holes in the dielectric during negative-bias
during negative-bias stress in the stack. Furthermore, the maxi-
mum depletion capacitance is observed to decrease during CVS of
the capacitors, as depicted in Fig. 12. This decrease can be attributed
to the reduction in the density of active boron acceptor impurities in
the p-type Si substrate, resulting from the formation of B–H
2
7,30
CVS may be either valence band tunneling ͑VBT͒
injection ͑AHI͒.
or anode hole
30,31
For the VBT mechanism of holes, the oxide
+
ot
positive charge generation probability Pgen = ⌬N /⌬N should not
inj
depend on stress voltage. This is because of filling of the pre-
existing hole traps. Pgen is also shown in Fig. 11 as a function of the
injected electron density Ninj during the negative-bias CVS in both
capacitors. As evident in Fig. 11, irrespective of the dielectric stacks,
3
3
complexes. Such complexes are induced by the transport of hydro-
gen in the Si substrate, consistent with the picture involving the
release of hydrogen during CVS. We therefore propose that bulk
oxide positive charges in the HfAlO dielectric stack are attributed to
holes and proton-induced defects. However, the contribution of
proton-related defects is significantly larger than that of holes in
oxide positive charge buildup. Recently, from the bias temperature
stress
Pgen strongly depends on Vg , which in turn is related to the elec-
tron energy reaching the anode. Moreover, for VBT to be a possible
mechanism, trapped oxide positive charge buildup should saturate
during stress consistent with the filling of pre-existing traps. How-
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H666
Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
stress
1
0
HfAlO
EOT ~ 2.6 nm
HfAlO capacitor
EOT = 2.63 nm
Vg
@
0
.0
-
4.25 V
-
4.0 V
-
-
0.2
0.4
1
Symbols: Expt.
Lines: Proton Transport Model
CVS@ -3.75 V
CVS@ -4.0 V
0
.1
01
102
103
104
102
103
104
1
Stress Time (s)
Stress Time (s)
Figure 12.
Cdep͑0͔͒/Cdep͑0͒ of an nMOS capacitor as a function of stress time during
CVS.
Relative maximum depletion capacitance ͓Cdep
Figure 13. Variation in trapped oxide positive charge density in HfAlO
capacitors with stress time during CVS at various voltages. Symbols are
from measurements and curves are from dispersive proton transport model.
−
stress measurements in HfO and SiO devices, we have identified
2
2
here. The process flow of the HfO devices can be found
2
+
these proton-related defects as the overcoordinated ͓Si v OH͔
35
2
elsewhere. Al incorporation in HfO introduces more oxide fixed
2
centers. Both ⌬N+ and ⌬D follow a t ͑n Ϸ 0.2͒ power law for
1
3
n
ot
it
charge and border trap in as-fabricated HfAlO samples when com-
both devices ͑Fig. 6 and 7͒, indicating the similar generation kinetics
pared with the virgin HfO devices of same EOT ͑not shown here͒.
2
14
for these two types of defects.
Like in HfAlO devices, HfO devices exhibit positive oxide charge
2
trapping during negative-bias CVS. A relative comparison of oxide
positive charge buildup rate in both devices is shown in Fig. 14a at
various equal stress voltages. The principle of operation of charge
trapping memory devices is closely related to the oxide charge
Model.— During negative-bias stress, the injected electrons are
transported toward the Si/SiO interface ͑anode͒ under the electric
2
field in the dielectric stack. These electrons acquiring energy above
the threshold energy for the liberation of hydrogen ͑proton͒ at the
Si/SiO interface depassivate Si w SiH centers, leading to the gen-
35
+
buildup in MOS capacitors. Therefore, the larger value of ⌬N at
ot
2
3
a given stress voltage, as depicted in Fig. 14a, indicates better per-
formance of charge trapping memory devices with HfAlO dielectric
when compared with HfO /SiO stack of same EOT. Unlike the
eration of trivalent Si w Si* dangling bonds acting as the interface
3
4
states and the subsequent release of hydrogen ͑proton͒. These lib-
2
2
erated protons are then accelerated toward the cathode ͑TaN gate͒
variation in ⌬N+ with stress time during CVS at an identical Vg
stress
,
ot
under the oxide electric field E , leading to the breaking of the
ox
the amount of ⌬Dit is more in HfO2 capacitors compared to the
+
bridging oxygen bonds and subsequent trapping of H by the
5,13
HfAlO capacitors, as illustrated in Fig. 14b. Nearly an equal number
strained Si–O–Si bonds
forming oxide positive charges. A frac-
10
−1
−2
͓
͑2 − 3͒ ϫ 10 eV cm ͔ of D was observed in both as-
it
tion of the liberated hydrogen, while accelerated toward the cathode,
3-5
fabricated devices. Results shown in Fig. 14b indicate that addition
generates neutral traps in the high-␬ layer. In the framework of
4,28
of Al increases the Si/SiO interface stability in HfAlO devices
2
the dispersive proton transport model,
oxide charge buildup by
one can model positive
during CVS. Coulombic scattering due to interface-trapped charges
36
plays a vital role in channel carrier mobility degradation. In view
+
+
⌬
N ͑t͒ = NoxT͕1 − exp͓− ␴͑H ͒͑t͔͖͒
͓11a͔
͓11b͔
of this, stress-induced channel carrier mobility degradation and
ot
bulk
G͑y͒dy
+
I͑t͒
+
bulk
+
int
͓
H
͔ = ͓H ͔ 1 −
ͫ
͵
ͬ
stress
Open: HfAlO
Filled: HfO2
EOT ~ 2.6 nm
Open: HfAlO
Filled: HfO2
EOT ~ 2.6 nm
0
5
4
3
2
1
0
V
g
@
0.4
0.3
-4.0 V
+
͓
H ͔ = ͓Si w SiH͔͓1 − exp͑− ␴ N ͔͒
͓11c͔
-4.25 V
int
3
H
inj
CVS@ -4.0 V
CVS@ -4.25 V
where NoxT is the total density of strained bonds in the SiO layer, ␴
2
0.2
+
~t
is their mean trapping cross section, and ͓H ͔ is the bulk concen-
tration of proton at a time t and is related to the instantaneous hy-
drogen concentration at the interface ͓H ͔ by the transport equation
bulk
+
int
0
0
.2
.1
͑
Eq. 11b͒. G͑y͒ is a trial function related to the probability of finding
a proton at a given distance from the interface at a given time t and
3
4
ᐉ͑t͒ is related to the dispersiveness of proton transport. ͓Si3
w SiH͔ is the initial concentration of passivated SiH bonds that
+
after depassivation yields H with a liberation cross section ␴
+
and
H
(a)
(b)
Ninj is the number of injected electrons per unit area. Figure 13
shows that the above proton transport model can well reproduce the
measured density of oxide-trapped positive charges during CVS in
HfAlO capacitors.
0.0
10
1
02
103
104
1
2
3
4
10
10
10
Stress Time (s)
Stress Time (s)
Figure 14. Number of stress-induced ͑a͒ positive oxide-trapped charges
Comparison between HfAlO and HfO devices.— To compare
the carrier trapping related deterioration of the gate stack and device
+
2
⌬N and ͑b͒ interface states ⌬D as a function of stress time in HfAlO/SiO
ot
it
2
͑open symbols͒ and HfO /SiO ͑solid symbols͒ stacks during CVS. Results
2 2
performances, HfAlO and HfO capacitors of equal EOT were used
are shown relative to the fresh devices.
2
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Journal of The Electrochemical Society, 156 ͑8͒ H661-H668 ͑2009͒
H667
stress
is approximately equal to voltage drop across the HfO layer, while
2
Vg
= - 4.0 V
-
-
-
-
-
-
600
500
400
300
200
100
0
EHfAlO Ͼ EHfO2 because of the larger physical thickness of the HfO2
layer. Therefore, at a given stress voltage, neutral trap creation rate
in the high-␬ layer is higher for HfAlO capacitors when compared
HfAlO
HfO
2
0
.2
100
~
t
Open: HfAlO
with HfO capacitors of same EOT.
2
EOT ~ 2.6 nm
Filled: HfO2
EOT ~ 2.6 nm
Conclusions
A systematic experimental investigation on the electrical stress-
induced degradation of gate dielectrics and device performances
with HfAlO gate dielectric is presented. We propose that dielectric
degradation is a composite effect of neutral trap creation, surface-
1
0-1
stress
Vg
= -4.0 V
sense
Vg
-
-
-
2.2 V
2.475 V
2.75 V
state generation at the Si/SiO interface, and positive charge trap-
2
ping in the bulk. Significant amount of border-trapped charges was
observed in both as-deposited and poststressed devices. Similar ki-
netics of generation of both oxide-trapped charges and interface-
trapped charges was observed. Both these defects are possibly re-
lated to hydrogen-related species. Furthermore, the results
(
a)
(b)
10-2
1
02
103
104
10-2
10-1
100
2
Qinj (C/cm )
Stress Time (s)
demonstrate that HfAlO samples are superior to HfO samples of
2
Figure 15. ͑a͒ Threshold voltage shift ⌬VT relative to the fresh device as a
function of stress time and ͑b͒ normalized SILC as a function of injected
electron fluence Qinj in HfAlO/SiO2 ͑open symbols͒ and HfO /SiO ͑solid
equal EOT in charge trapping memory and CMOS logic applications
at the cost of shorter device lifetime and enhanced gate dielectric
deterioration due to excess oxide charge buildup and neutral trap
2
2
sense
symbols͒ stacks after CVS at −4.0 V with sensing voltage Vg as a param-
stress
eter.
creation in HfAlO capacitors at a given Vg . The present study
gives an important message that bypassing the leakage current ben-
efit due to Al incorporation in HfO , a trade-off between the device
2
performance and dielectric degradation assessing the oxide reliabil-
ity must be made in selecting the appropriate gate stack of a given
EOT.
transconductance ͑g ͒ degradation in metal oxide semiconducton
m
field-effect transistor ͑MOSFETs͒ with HfAlO gate dielectric are
lower than that with HfO of an equal EOT. Similar observations
were experimentally observed by Joo et al. in their MOSFET de-
2
7
Acknowledgment
vices.
P.S. thanks Dr. Souvik Mahapatra at Microelectronics Division,
IIT, Bombay, for providing the measurement facilities. The authors
thank the National Science Council of Taiwan for the financial sup-
port under contract no. NSC 97-2221-E-150-072. Technical support
from National Nano Device Laboratories ͑NDL͒ of Taiwan is also
acknowledged.
At a given operating voltage, the higher VT degradation in
HfAlO capacitors, as depicted in Fig. 15a, shortens the device life-
time compared to the devices with HfO /SiO stack of same EOT.
2
2
In other words, for a given projected lifetime within a given toler-
ance of V shift, the operating voltage of the HfAlO devices would
T
be lower than that of the HfO devices with an identical EOT. ⌬V
2
T
National Formosa University assisted in meeting the publication costs of
this article.
comprises of ⌬N+ and ⌬Dit.+ Therefore, comparing the results
35
ot
shown in Fig. 14 and 15a, ⌬N significantly contributes in V deg-
ot
T
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2
1
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1
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the electric field in the high-␬ layer in either of the capacitors. For a
stress
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+
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E ͑HfAlO͒ Ͼ E ͑HfO ͒. Therefore, the density of ⌬N is larger
ox
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2
stress
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