Full text of DOI:10.1007/s11837-001-0103-y

Microelectronic Processing
Overview
Copper Interconnects for
Semiconductor Devices
Sailesh M. Merchant, Seung H. Kang, Mahesh Sanganeria, Bart van Schravendijk, and Tom Mountsier
Copper/low-k dielectric materials have
been rapidly replacing conventional alumi-
Increasing RC values have prompted
a flurry of activity in the design and
process communities. To lower the ca-
pacitance, new insulators and methods
of processing with materials having
lower dielectric constants (k < 4) have
shown promise. To lower the resistance
of metal lines, the industry turned to a
materialoflowerresistivity,namelycop-
per, with a resistivity less than 2 mW-cm.
Reductions in both the dielectric con-
stant and metal resistivity have helped
reduce the number of metal layers re-
quired for optimal chip performance.
Circuit-designmodelshavehelpediden-
tify critical path interconnects, provide
optimal layouts, and avoid over-design.
NowherehaveimprovementsintheRC-
product been more useful than in high-
performance devices such as micropro-
cessors. The requirements of such de-
vices have necessitated drastic changes
in interconnect materials and, in re-
sponse, the industry has been quick to
adopt copper as an alternative to alumi-
num alloys.
num-alloy/SiO -based interconnects in
2
today’s semiconductor devices. This paper
reviews the advantages of transitioning to
copper/low-k interconnects. Materials and
process challenges during the fabrication of
devices with copper/low-k interconnects are
discussed. Reliability concerns associated
with such devices are highlighted.
Figure 2. A general dielectric stack used in
dual damascene process flow.
INTRODUCTION
have been introduced in the manufac-
turing line. For example, metal etch pro-
cesses, critical for aluminum alloy inter-
connects, have been completely elimi-
nated. However, newer processes such
as damascene and dual damascene fab-
rication and electroplating have created
newchallengesfortheprocessengineer.
The most common process integration
steps to form copper interconnects
For the last thirty years, aluminum
alloy metallization has remained the
workhorse of the semiconductor indus-
try in fabricating interconnects for the
production of integrated circuits. Alu-
minum alloys have low resistivity (3.0–
5
.0 mW-cm) and are amenable to low-
cost, high-throughput fabrication pro-
cesses. Because these alloys are able to
form a passivating oxide film, they can
be easily patterned and etched. More-
over, aluminumalloysshowgoodadhe-
sion to most dielectrics used in the in-
dustry. While early devices were made
with an all-aluminum-alloy metalliza-
tion scheme, much of the industry mi-
grated to tungsten plugs for contact and
via fill at the 0.5 mm technology node,
and aluminum alloys served only as in-
terconnects. When used in conjunction
with refractory cladding materials such
as titanium and titanium nitride (TiN),
aluminum alloys exhibit enhanced reli-
ability such as resistance to stress-in-
duced voiding and electromigration.
Therefore, theindustryhasoptedtostay
with aluminum alloy metallization and
hasextendedthelifeofaluminumalloys
to the 0.25 mm technology node.
5,12,13
are
• Deposit the damascene or dual
damascene interlevel or intermetal
dielectric. This dielectric may be
multi-layeredandmayincludeetch
stops such as silicon nitride. The
Copper was first reported to be an
alternativetoaluminumalloymetalliza-
tion in the fabrication of integrated cir-
dielectric
may
require
a
planarization step using CMP.
5
,6
cuits in 1997 . Since then, knowledge of
process requirements and reliability is-
sues associated with copper intercon-
nects has grown significantly. This pa-
perreviewsprocessandmaterialsissues
associated with the fabrication of silicon
semiconductor devices containing cop-
per interconnects.
• Pattern and etch the damascene or
dual damascene structure into the
dielectric.
• Filltheopeningswithelectrodepos-
ited copper. A barrier/seed stack is
depositedpriortoelectrodeposition.
• Anneal the wafers to stabilize the
microstructure and avoid second-
ary recrystallization effects.
• Polishtheexcesscopperandbarrier
away using CMP.
• Repeat steps 1 through 5 for multi-
layered interconnects.
• PassivatethefinalCopperlayer,and
prepare the chip for packaging and
assembly.
Successful integration of copper into a
dual damascene structure requires sev-
eral critical steps that will be discussed
in the next sections.
FABRICATION PROCESSES
FOR COPPER INTERCONNECTS
With the introduction of copper met-
allization, new fabrication processes
With ever-increasing demands to
shrink dimensions of microelectronic
devices, interconnect scaling has made
limited advances in high-performance
1–3
integrated circuits. Interconnect resis-
tance and capacitance (also known as
RC-product) have become important
parameters in determining integrated
circuitdesign,designrules,packingden-
sity, and device performance. For sub-
DIELECTRIC FILM
DEPOSITION
0.25mmtechnology,theinterconnectRC-
product, not the intrinsic gate delay, has
become dominant in determining over-
all device performance. Interconnect
delays must be minimized due to ever-
increasing needs for faster devices with
The most commonly used dielectric
material in multilevel metallization is
undoped silicate glass (USG) with a
nominal dielectric constant of 4.1. As the
industry moves from the 0.25 mm tech-
nology node to 0.18 mm, some semicon-
Figure1.Relationshipbetweendielectriccon-
stant and hardness of dielectric materials.
4
low power consumption.
2
001 June • JOM
43

1
,000 Å. The diffusion barrier and etch-
stop material was assumed to be Si N4
3
with a dielectric constant of 7.0. The
simulations were performed with via
and trench dielectric materials with di-
electric constants 2.2, 2.7, 3.5 and 4.1
representing four nodes of technology.
As shown in Figure 3a–b, the effective
dielectricconstantincreasesasthediffu-
sion barrier and etch-stop thickness is
increased. Also, the increase in effective
dielectric constant is substantially more
when the etch-stop layer is present. For
example, for a material with a dielectric
constant of 2.2, the increase in effective
dielectricconstantis47%whenbothetch
stop and diffusion barrier layers are
present, however, the increase is only
Figure4. Illustrationofeffectofsubstratetype
on resist profile.
able OSG film produced using a propri-
TM
etary precursor, SiCOH A (CORAL ),
providesaharderfilmcomparedtofilms
prepared using tetra-methyl silane
a
(
4MS)/tri-methyl silane (3MS) as a pre-
cursor. For the same dielectric constant,
film deposited using the proprietary
precursor has less carbon compared to
film deposited using 4MS/3MS. As a
result, higher hardness is achieved for
the proprietary precursor at the same
value of dielectric constant. On the other
hand, asshowninFigure1, thehardness
ofapolymericfilmproducedusingspin-
on technique is substantially lower than
the films produced by PECVD.
2
3% when the etch-stop layer is not
present. Also, it is clear from Figure 3a
that the effect of diffusion barrier and
etch stop is more pronounced when the
dielectric constant of the trench and via
dielectric is lower.
The fourth layer in the dielectric stack
showninFigure2isthetrenchdielectric.
The dielectric constant of this material is
the most important parameter in deter-
mining the RC delay of the circuit. As
deposited film dielectric constant and
any modification during subsequent
processingshouldbecarefullycontrolled
to achieve the desired device speed. The
final and the topmost layer is the cap
layer. It may be used in the stack for
several reasons—as an anti reflective
coating, as a stop layer for metal CMP,
and/or as an etch-stop layer during via
etch to counter resist consumption.
Again,alleffortsarebeingmadetoavoid
using a cap layer, or remove it before the
deposition of subsequent layers to re-
duce the effective dielectric constant of
the film stack.
b
DIELECTRIC FILM STACK
Figure 3. Normalized effective dielectric con-
stant as a function of diffusion barrier thick-
ness (a) with etch stop, and (b) without etch
stop.
Figure 2 shows a general dielectric
stack used in the dual damascene pro-
cess flow. The bottom layer is used both
as a copper-diffusion barrier and as an
etch-stop layer for via etch. Materials
being used for this application are
PECVD silicon nitride (Si N ) and sili-
ductor manufacturers have used fluori-
nated silicate glass (FSG) films to reduce
the dielectric constant to between 3.6
and 3.8. FSG presents serious integra-
tion challenges due to its susceptibility
to moisture absorption, however, the
mechanical strength of FSG is sufficient
to enable successful integration. Also,
FSG can be deposited in a conventional
plasma-enhanced chemical vapor depo-
sition (PECVD) reactor or in a high den-
sity plasma chemical vapor deposition
reactor with minor modifications.
3
4
con carbide (SiC). The Si N can be de-
3
4
posited with a dielectric constant in the
range of 6.5 to 7.0 whereas much lower
dielectric constants in the range of 4.0 to
4.5 can be achieved for SiC. The next
layerfromthebottomistheviadielectric
layer. The third layer is used as trench
etchstop(ES).Usuallythesamematerial
is used for the diffusion barrier and the
etchstop.Thisetch-stoplayerprovidesa
good trench bottom profile. Efforts are
being made to eliminate ES layer to ob-
tain lower effective dielectric constant.
Elimination of the ES layer will require
improving the trench etch process to
provideaflatbottomprofilewithoutthe
ES layer. The significance of eliminating
the trench etch stop layer is illustrated in
Figure 3, which shows
For the 0.13 mm technology node, a
dielectric material with a bulk dielectric
PATTERNING OF DUAL
DAMASCENE STRUCTURES
1
4
constant of 2.7 is required. The pre-
ferred material to meet this requirement
has been organo-silicate glass (OSG) or
carbon-doped silicate glass. This mate-
rial,however,ismarkedlydifferentfrom
USG. OSG can be deposited to give a
wide range of dielectric constant values,
but as the dielectric constant decreases,
hardness decreases concomitantly.
Lower hardness films present serious
integration challenges as a result of
lower adhesion to other films, CMP in-
compatibility, dimensional instability,
and problems in packaging.
Figure 1 shows the relationship be-
tween hardness and dielectric constant
of some known dielectric materials be-
ing used or evaluated for multilevel
metallization. The challenge in deter-
mining the film of choice is maximizing
hardness for a given dielectric constant.
Two main factors determine the hard-
ness of low-k material: the precursor for
deposition and the deposition method.
AsseeninFigure1,acommerciallyavail-
The formation of dual damascene
structurerequirestwolithographysteps:
defining via and defining the trench.
Dual damascene structures have been a
the normalized effective
dielectric constant as a
function of the diffusion
barrier layer and/or ES
filmthicknessembedded
in materials with differ-
ent dielectric constants.
The effective dielectric
constants were calcu-
lated using the Raphael
simulation software
Unexposed
Pad Area
Exposed Pad Area
1
5
package. The total di-
electric stack thickness
wasmaintainedat1.0mm
for all cases. The diffu-
sionbarrierandetch-stop
layer thickness used
were 0, 500 Å, 700 Å, and
▲
Poisoned Photoresist
26 mm
Figure 5. Plan view SEM illustrating poisoned resist in via after
trench lithography.
4
4
JOM • June 2001

key enabling technology for advance-
ment of the use of optical lithography
The consequence of resist poisoning
during trench lithography is illustrated
schematicallyinFigure6.Figure6shows
a cross-section through a via chain link
at three stages of dual damascene pro-
cess flow: after trench lithography, after
trench etch, and after resist strip. Figure
6a represents the case when resist poi-
soning is present. In this case, the poi-
soned resist looks like a mushroom in
thecross-section.Themushroom-shaped
photoresist will mask the dielectric dur-
ing trench etch. Figure 6b shows the
desired resist profile for a via chain link
without the resist poisoning. It is clear
from the previous illustration that resist
poisoning must be eliminated for the
formation of a successful dual dama-
scene structure. It should be noted that
low-k materials are prone to resist poi-
soning because of their porous nature.
They tend to absorb contaminants dur-
ing various processing steps that subse-
quentlypoisonthedeepUVphotoresist.
Copper metallization and low dielec-
tric constant materials have created nu-
merous challenges for plasma-etch pro-
used as a trench etch-stop layer in some
schemes. As the dielectric constant of
Si N is significantly higher than SiO , or
1
6–18
for today’s semiconductor devices.
3
4
2
To address depth-of-focus issues, opti-
calproximitycorrectionandphase-shift-
ing masks are being increasingly uti-
lized in extending the present lithogra-
phy tool capabilities. The industry is
now working on the next generation 193
nm and 157 nm tools that will allow
printingdowntothe0.07mmnodeusing
optical lithography.19 Deep ultra violet
low k, materials, the Si N layers should
3 4
be made as thin as possible. Thus, etch
processesmust, ingeneral, possessquite
high selectivity with respect to Si N .
3
4
Furthermore, while removing the bar-
rier Si N , great care must be taken to
3
4
avoid oxidizing and/or sputtering the
copper underneath. When other materi-
als are used for etch-stop and barrier
layers, the above constraints on the di-
electric etches still apply.
(
UV) photoresist is being used for 0.13
mmtechnologynodewherelowkdielec-
tric material is being introduced. Deep
UVphotoresistuseschemicalamplifica-
tion which makes it very sensitive to the
substrate. Chemical amplification re-
quires the right amount of photo-gener-
ated acid atoms. A basic substrate can
cause resist footing by depleting photo-
generated acid, whereas an acidic sub-
strate can result in resist pinch-off by
supplying more acid than needed, as
Besides OSG materials, polymeric
materials are also candidates for ad-
vanced interconnect systems with low
dielectric constants. In these materials,
carbonaceous material in the film must
be volatilized in order to effect the etch
process. This requirement typically re-
duces selectivity with respect to photo-
resist. In the case of polymeric materials,
the solution is to utilize a hard mask
2
0
illustrated in Figure 4. This problem is
exacerbated during trench lithography,
where the photoresist fills via holes. Ba-
sic contaminants, primarily amines in
the as-deposited film or incorporated in
the film during subsequent processing,
diffuse into the photoresist and neutral-
ize the photo-generated acids necessary
for resist development. This neutraliza-
tion of photo-generated acids, also
known as resist poisoning, Results in
resist caps remaining in via holes even
aftertheresistdevelopmentprocess.Fig-
ure5showsatopviewscanningelectron
micrograph of an array of vias in the pad
area after trench lithography. The hemi-
sphericalshapedresistremaininginvias
after trench lithography is the result of
resist poisoning.
(typically SiO ) alone or in conjunction
2
witharesistmask. Chemistriestypically
used to etch polymeric films include ni-
trogen mixed with hydrogen or oxygen.
Often, a passivant gas is added as well,
typically in the form of C H , which aids
2
1,22
cess engineers.
A plethora of new
interconnect integration schemes and
new dielectric materials must be etched.
Furthermore, as the new interconnect
systems are applied to advanced tech-
nology nodes with ultra-high packing
density, thesesystemsoftenrequireetch
processes to perform at unprecedented
feature-aspect ratios and degree of di-
mensional control. When copper metal-
lization is applied in conjunction with a
x
y
in producing an anisotropic etch. Etch
chemistriesforOSGmaterialsaregener-
allybasedonanoxideetchrecipe, which
utilizes fluorocarbons and hydrofluoro-
carbons as the primary etchants, with an
extra gas added to form volatile com-
pounds with carbon. This carbon-vola-
tilizing additive is chosen so that it will
notattackthesidewallpassivationinthe
etched feature. Such an attack would
render the etch process isotropic.
conventional SiO dielectric in a dual-
2
damascenescheme,thereareseveralkey
challenges. Often, Si N is used as a bar-
3
4
rieroverthecopperinterconnecttowhich
the etched vias will connect, and is also
A common practice to remove photo-
resist after etch is to subject the wafer to
BACKGROUND ON COPPER INTERCONNECTS
Because copper’s resistivity is lower than that of
aluminumalloys,itallowshighercurrentdensities,even
for reduced cross-sections of conductors. More impor-
tantly, copper metallization has shown a dramatic im-
etch techniques. Therefore, damascene or dual
damascene fabrication techniques have become
mandatory for fabricating devices with copper.
Unlike aluminum, copper does not form a self-
passivating oxide, so it readily oxidizes (and cor-
rodes) even in the clean room ambient at low
temperatures. Thus copper exposed at the top of
vias or trenches needs to be protected. This oxide
must be removed (or at least reduced) prior to
making connections to other metal layers.
Copper is an aquatic toxin and therefore, several
environmental, health, and safety issues need to
be addressed.10 Copper-containing liquids such
as slurry from chemical-mechanical polishing
(CMP),consumedelectroplatingsolution,andrinse
water must be properly handled during waste
disposal and suitable effluent treatment equip-
ment is required.
aluminum-alloy processing and copper, copper-dedi-
cated tools are recommended after damascene struc-
tures have been formed at the first dielectric level. All
metrology tools that are used to measure copper-
containing wafers must be dedicated, and other tools in
the line that do not process copper wafers must be
monitored routinely for copper contamination. For ex-
ample, routine monitoring of wet benches, gate oxide
and diffusion furnaces, and associated front-end me-
trology tools becomes mandatory. To save money,
some fabrication lines share lithography tools for cop-
per and aluminum back-end metallization. Again, cop-
per levels in these tools must be carefully monitored
when switching between copper and non-copper pro-
cessing modes. A wafer backside barrier material such
as silicon nitride is recommended. Any thermal expo-
sure of the wafer during routine processing may cause
copper to migrate through the wafer backside into the
active regions of devices. Copper-dedicated cassettes
and boxes for copper-containing wafers are suggested.
Analytical facilities need to be updated with tools that
accuratelymeasurecoppercontaminationlevels.More-
over, all fabrication line personnel must be trained, and
an escalation procedure established, to cope with con-
tamination. Information systems used for lot tracking
and wafer management need to be modified to help
minimize the risk of contaminating non-copper equip-
ment.
∑
∑
5–
provement(10–100X)inresistancetoelectromigration
8
6
andstress-inducedvoiding. Anewapproachtocreate
inlaid structures of copper using damascene or dual
9
damascene methods has made fabrication of devices
with copper feasible. The availability of low cost, high-
throughput processes such as electroplating has per-
mitted the fabrication of these in-laid structures. More-
over, once the industry completely migrates to copper,
fabricating devices with copper will likely be cheaper
than ones with the conventional W/Al alloy metalliza-
tion. However, selecting copper as an interconnect
metal is difficult for the following reasons:
∑
Copperdiffusesveryrapidlyinsiliconandconven-
tional dielectrics, and if not checked, can cause
severe threshold-voltage shifts and junction leak-
age. Because copper can cause inter- and intra-
level shorts, it must be encapsulated on all sides
with barrier layers. The encapsulation has to be
repeated for all levels of copper metallization.
Copper lines cannot be easily patterned like those
made of aluminum alloys. The lack of volatile
byproducts does not allow easy etching of copper
lines using conventional (subtractive) reactive ion
Copper Protocol and Contamination
Anotherpotentialdrawbackofcoppermetallizationis
contamination. Adevice-fabricationlineshouldbededi-
cated to copper processing; aluminum-alloy metalliza-
tion should be conducted in a separate line. Otherwise,
manufacturing protocol will have to be re-engineered to
control copper contamination in the line.11 Although
front-end tools may be shared for both conventional
∑
2
001 June • JOM
45

An ideal barrier must be free of defects,
smooth, continuous, and conformal at
minimalthickness.Thebarriermusthave
good adhesion and show no interaction
with dielectrics and the seed layer. In
some cases, an adhesion layer may be
deposited prior to barrier-layer deposi-
tion. The barrier must be CMP-compat-
ible and should not delaminate or crack
because of mechanical stresses during
processing. A dense, amorphous barrier
is preferred to avoid fast diffusion paths
for copper, such as grain boundaries.
The barrier behavior of TaN to copper
interdiffusion has been studied. The
authors show that TaN resistivity and
composition can be tailored by adjust-
ing the nitrogen flow introduced into
the plasma during deposition. Barrier
behavior of TaN films was studied by
fabricatingcapacitorstructureswithcop-
per and tested at 2MV/cm at tempera-
tures between 200–275∞C. TaN films
show good barrier performance in these
test conditions.
a high pressure (approximately 1 torr)
oxygen plasma in the etch tool. How-
ever, this technique cannot be used for
OSG materials. Oxygen reacts with the
carboninOSGfilmanddepletesthefilm
of carbon, which may result in severe
cracking of the film. Figure 7 shows a
secondaryionmassspectroscopy(SIMS)
profile of oxygen, carbon, and silicon
through an OSG film subjected to an
oxygen plasma treatment in an ashing
reactor. The SIMS profile clearly shows
substantial carbon depletion in the top
0
.2 mm OSG film. These results suggest
2
6
Figure 7. SIMS profile of oxygen, silicon, and
carbon of an OSG film exposed to high pres-
sure oxygen ashing chemistry showing car-
bon depletion.
that conventional ashing technique can-
not be used for OSG material.
BARRIER AND SEED LAYERS
The barrier materials for copper that
have been reported are generally refrac-
tory metals or refractory metal nitrides.
Early studies used TiN as a barrier
stack,5 but now most companies have
settled on tantalum-based barriers. Of
tration of the bath, becomes critical. On-
board closed-loop analysis and chemi-
calreplenishmentsystemsarenowcom-
merciallyavailablethatmakebathchem-
istry control a routine operation.31
,23
Feature-fillmechanismshavebeenre-
24
25,26
these,tantalum andTaN arethemost
common materials used today and are
typically deposited using hollow cath-
3
2
The importance of adequate seed
conformality and coverage cannot be
overemphasized. If the seed coverage in
a dual damascene structure is discon-
tinuous, then feature fill during copper
electroplating becomes difficult and
voids will typically be observed along
the feature sidewalls.
viewed. Of these, superfilling, or fill-
ing of vias or trenches from the bottom
up rather than from the sidewall, is de-
fined to be the ideal fill technique. Sig-
nificant improvements in the fill capa-
bility have been reported by optimizing
plating waveform and custom additive
27
odemagnetron orionizedmetalplasma
26
(
IMP)deposition. Othermaterialssuch
as tungsten nitride and ternary refrac-
tory barriers such as Ta-Si-N have also
28
beeninvestigated. Acomparisonoftan-
talum, TaN, and Ta-Si-N barriers for
copper interconnects has been recently
reported.29 A listing of various barriers
for copper from previous studies is dis-
cussed in Reference 30.
3
3
chemistry. Itwasshownthatfillinhigh
aspect-ratio via was limited due to the
formation of bottom and center void
defects. These defects were eliminated
by improving the bottom-up selectivity
of the plating process.
Astheindustrymigratestowardshigh
aspect-ratioopenings,conventionalbar-
rier/seed deposition techniques such as
IMP will likely be inadequate to provide
conformal coverage in features. There-
fore, process engineers are trying to use
chemical vapor deposition (CVD) meth-
ods for barrier and seed layer formation.
Although the resistivity of copper is
significantly lower than that of alumi-
num alloys, the effective resistance of a
copper line is determined by the actual
cross-section of the line itself. Therefore,
barriers used for encapsulating copper
must be as thin as possible and those
with high resistivity should be avoided.
Electrodeposited copper films are
unique in that a dramatic evolution of
film microstructure is observed at room
temperature immediately following
deposition.Thismicrostructuralchange,
referred to as secondary recrystalliza-
3
1
A recent study has shown complete
feature fill using CVD-WN and CVD-
copper prior to copper electroplating in
3
4
0
.18 mm diameter features with an as-
pectratioof9:1.Recently,
chemical vapor deposi-
tion techniques have
been used to deposit Ti-
Si-Nasabarriermaterial
to allow conformal cov-
erageindualdamascene
structures.
tion, includes an increase in grain size,
a decrease in resistivity and hardness,
andchangesinstress,withahighdegree
of twinning. Moreover, changes in pre-
ferred crystallographic texture (orienta-
tion) of the deposited film have been
3
5
observed. Texture in damascene
trenches has been investigated.3
These changes in microstructure have
been attributed to high stress and dislo-
cations in the film, which in turn are
related to additives in the electroplating
4,36,37
ELECTROPLATED
COPPER
3
4–37
Copper sulfate-based
electrolytes are used to
electrodeposit copper in
damascene or dual
process.
It is advisable to include an
a
intermediate anneal step to present a
consistent microstructure for CMP pro-
cessing after electroplating copper.
3
1
damascene features.
A
RELIABILITY
varietyofchemicalssuch
asinhibitors,accelerants,
and brighteners, added
to the bath for improved
and consistent fill, make
understanding feature
fillmechanismsdifficult.
Moreover, control of
these additives, includ-
ing the copper concen-
It has been recognized that copper is
superior to aluminum against electro-
migration (current-induced diffusion),
which has been a major reliability con-
cern in the manufacturing of microelec-
tronicinterconnects.Copper,withlower
resistivity than aluminum, in principle
canprovidehigherelectriccurrentsfora
given voltage, leading to a faster inte-
b
Figure6. Schematiccrosssectionofaviachainlinkaftertrench
lithography,trenchetchandresiststrip:(a)withresistpoisoning
and (b) without resist poisoning.
4
6
JOM • June 2001

grated circuit (IC) without sacrificing its
reliability against electromigration.
However, this anticipated electromigra-
tionreliabilityisoftendifficulttoachieve
as the industry migrates to sub-0.2 mm
wide copper lines integrated with ultra-
thin diffusion barriers and low-k dielec-
tric materials. In addition, the useful
lifetime of the IC can be limited by other
reliability concerns, such as copper dif-
fusion in surrounding dielectrics, me-
chanical instability, corrosion, and Joule
heating. This paper addresses some of
the reliability issues related to electro-
migration and time-dependent dielec-
tric breakdown under bias-temperature
stress (BTS).
is encouraging and may justify a higher
current operation at chip-use conditions
(T approximately 110∞C) provided that
the following criteria are satisfied. First,
the activation energy and the current-
density acceleration factor for copper
electromigration are comparable with
those for aluminum alloys. Second, the
failure-time distribution (described by a
log-normal curve) for copper is as nar-
row as that for aluminum alloy, that is,
the deviation in time-to-failure (known
as s) for copper is comparable with that
for aluminum alloy. These criteria ne-
cessitate an identification of a primary
electromigrationfailuremechanismand
an understanding of its sensitivity to
microstructural and process variations.
However, the electromigration mecha-
nism for damascene copper intercon-
nectsisnotclearlyunderstood.Recently,
However, this diffusion barrier is much
thinner than the films used for alumi-
num; its actual thickness along the
sidewallandbottomofthecoppertrench
is often less than 10 nm. Hence, its cur-
rent-shunting effect is rather limited so
that the rate of resistance increase due to
voidingforcopperinterconnectsislarger
than the rate for aluminum. Conse-
quently, the size of a void that causes
failure is substantially smaller for cop-
per interconnects than that for alumi-
num interconnects. It is expected that
this will become a more serious problem
for ICs with smaller feature sizes.
Copper metallization must also be re-
liable against time-dependent dielectric
breakdown under bias-temperature
stress (BTS). It has been well recognized
that copper ions can rapidly diffuse
through dielectrics to cause a short cir-
cuit. This is a concern particularly with
anintegrationoflow-kdielectricmateri-
als since their dielectric breakdown
strength appears to be lower than that of
Prior work reported that the mean
time-to-failure for copper interconnects
(
usedfor0.25mmtechnology)wasabout
two orders of magnitude longer than
thatforaluminumalloywhentheywere
3
8
Hu et al. have reported that, in the case
of narrow copper interconnects, surface
diffusion (e.g., along the copper-SiN
overlayer interface), rather than grain-
boundary diffusion or intermetallic in-
terface diffusion (e.g., along the copper-
diffusion barrier interface), acts as a
2
testedatcurrentdensity, J=2.5MA/cm
and temperature, T = 295∞C. This result
6
SiO . To prevent copper diffusion under
2
BTS, the diffusion barrier must maintain
its functional integrity throughout the
useful lifetime of the IC. It seems that,
however, incorporating only a diffusion
barrier is not sufficient to ensure the
metallization reliability against time-
dependent dielectric breakdown. Prior
work reported that a preferable path for
copper diffusion is along the interface
between the intra-level dielectric (ILD)
surface and the passivation layer (cap-
38
dominantelectromigrationmechanism.
They have also reported that the activa-
tion energy of surface diffusion is 0.9
electron-volt (eV). This activation en-
ergy is larger than the activation energy
of aluminum alloy for grain-boundary
diffusion(0.7eV), comparabletothatfor
interface diffusion (0.9–1.0 eV), but
smallerthanthatforlatticediffusion(1.2
eV). It follows that, for bamboo lines
where grain boundaries are not active
diffusion pathways, copper does not
have an advantage over Al(Cu) from the
activation-energy perspective. Further-
more, the activation energy for copper
electro-migrationcanevenbelowerthan
0.9 eV if the quality of the copper surface
with respect to surrounding materials is
4
1
ping layer). Therefore, it is critical to
achieve a defect-free copper and ILD
surface particularly through chemical-
mechanical polishing and the passiva-
tion-layer deposition. It is also essential
tomaintaingoodadhesionbetweenthese
layers, even under BTS.
Time to Failure (h)
a
Finally, one of the most difficult reli-
abilitychallengesincopperinterconnect
manufacturing is to control early fail-
ures. The existence of early failures is
sensitive to process stability and varia-
tions. As illustrated in Figure 8, in some
cases, electromigration and BTS failure
distributions are bimodal due to the ex-
istence of early failures. Note that the
reliability of a chip against electro-
migration or BTS failure is determined
by the time at which the first failure in a
large set of lines occurs. The reliability
margin is then usually set to 0.01% or
0.1% cumulative failures. Hence, an in-
crease in mean time-to-failure does not
necessarily reflect a reliability improve-
ment. To ensure a high value of the time
to first failure, a method to improve the
reliabilitymustbeonethatnotonlyelimi-
nates early failures, but also promotes a
narrow failure distribution.
3
9
poor.
For aluminum-based interconnects, it
is well recognized that a refractory layer
like TiN and titanium is incorporated to
conduct electricity in the presence of a
void (known as a current-shunting ef-
fect). This film is about 30–50 nm thick
and coats the top and bottom surfaces of
the aluminum line. To improve
electromigration reliability, it is critical
to control the sheet resistance and the
thickness of the refractory film since the
rateofresistanceincreaseduetovoiding
is greatly affected by the architecture
4
0
and physical properties of the film. In
addition, this refractory film must be
defect-free since any discontinuity, for
example, a micro crack, will lead to a
catastrophic resistance increase in the
presenceofavoid.Similarly,thesidewall
and bottom surfaces of the copper line
are coated with a barrier film like Ta or
TaNtopreventcopperdiffusionthrough
dielectric films. This diffusion barrier
also serves as a current-shunting layer.
Time to Breakdown (s)
b
CONCLUSION
The future of copper interconnects for
semiconductordevicesispromising,but
some difficulties will have to be over-
Figure 8. Cumulative probability plot for
electromigration failure and bias temperature
stress failure showing early failures.
2
001 June • JOM
47

come. With decreasing dimensions and
increasing aspect ratios of dual dama-
scene structures, the barrier/seed cov-
erage will be an issue. Therefore, ultra-
thin, low resistivity amorphous barrier
layers, compatible with low-k dielec-
trics, will be required. Minimal contact
resistancerequirementswilldriveequip-
ment trends toward increasing in-situ
methods of deposition. Significant ad-
vances in electroplating tool chemistry
andtheuseofseedrepairtechniquesare
envisioned for the immediate future, as
are plating tools with multi-step reci-
pes. On-board bath monitoring and re-
plenishment techniques will be com-
monplace.
The selection of low-k materials will
most likely be based on process integra-
tion issues rather than material proper-
ties, facilitated by the advent of newer
etchchemistries.NewerCMPslurryfor-
mulations and pad designs to minimize
topography effects, dishing and erosion
will be required. Optical lithography
techniques are envisioned to serve till at
least the 0.10 mm technology node, with
phase-shift masks and optical proxim-
ity correction schemes being routine.
The system-on-a-chip concept will al-
lowintegrationofotherdevices, notjust
stand-alonemicroprocessors,wherecop-
per/low-k materials will be mandatory.
Copper metallization will become rou-
tine for application-specific integrated
circuit applications and will be intro-
duced in dynamic random access
memory. All these advancements will
be feasible only with decreased tool and
consumable costs, as copper enters the
manufacturing mainstream for ad-
vanced technologies and completely re-
places aluminum alloys.
11. T. Cacouris, Micro, 43 (July/August 1999).
12. P. Singer, Semicond. Int., 20 (9) (1997), p. 79.
3. P. Singer, Semicond. Int., 21 (6) (1998), p. 91.
1
14. Int. Technology Roadmap for Semiconductors, 2000 update
(
San Jose, CA: Semiconductor Industry Association, 2000).
TM
1
5. Raphael , Interconnect Analysis Software (Fremont, CA:
Avant! Corp., 1998).
1
1
1
1
6. P.J. Silverman, Future Fab Int., 7 (1999), p. 127.
7. J.A. McClay and J.J. Shamaly, in Ref. 16, p. 135.
8. A.M. Goethals and K. Ronse, in Ref. 16, p. 143.
9. J.A. McClay and A.S.L. McIntyre, Solid State Technology,
42 (6) (1999), p. 57.
2
1
0. C.P. Soo et al., IEEE Trans. Semiconductor Manufacturing,
2 (4) (1999), p. 462.
21. P. Singer, Semiconductor International, 22 (9) (1999), p. 68.
2. I. Morey and A. Asthana, Solid State Technology, 42 (6)
2
(
1999), p. 71.
23. K. Park et al., J. Appl. Phys., 80 (1996), p. 5674.
2
4. I. Hashim et al., Proc. SPIE, 3508 (1998), p. 58.
5. T. Oku et al., Appl. Surf. Sci., 99 (1996), p. 265.
2
ACKNOWLEDGEMENTS
26. B. Chin et al., Solid State Technology, 41 (7) (1998), p. 141.
2
7. K.A. Ashtiani et al., Proc. IEEE-IITC (2000), p. 37.
8. M. Nicolet et al., Appl. Surf. Sci., 91 (1995), p. 269.
Theauthorswouldliketoacknowledgethe
efforts of colleagues, peers and management
at Agere Systems and Novellus Systems,
Inc. Novellusauthorswouldliketoacknowl-
edge the Customer Integration Center at
Novellus Systems, Inc. for help with copper/
low-k integration work.
2
29. Q-T. Jiang et al., Proc. IEEE-IITC (1999), p. 125.
3
3
0. C. Ryu et al., Solid State Technology, 42 (4) (1999), p. 53.
1. A.E. Braun, Semiconductor Int., 22 (4) (1999), p. 58.
32. P.C. Andricacos, Interface, 8 (1) (1999), p. 32.
3
3
3
3
3. J. Reid et al., Proc. Adv. Metall. Conf., 99 (1999), p. 284.
4. C. Lingk et al., J. Appl. Phys., 84 (10) (1998), p. 5547.
5. J.M.E. Harper et al., J. Appl. Phys., 86 (5) (1999), p. 2516.
6. C. Lingk et al., Appl. Phys. Lett., 74 (5) (1999), p. 682.
37. M.E. Gross et al., Solid State Technology, 42 (8) (1999), p. 47.
8. C.-K Hu et al., Appl. Phys. Lett., 74 (1999), p. 2945.
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Sailesh M. Merchant and Seung H. Kang are with Agere
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Agere Systems, Orlando, Florida 32819; (407)
371-7538; agere.com.
9
1
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