In the transimpedance stage, the feedback impedance (Z) is a parallel
resistor and compensation capacitor. An NMOS transistor in triode
mode functions as the resistor, enabling gain adjustment through
modification of the gate voltage. The differential amplifier is based
on a two-stage design [5] with output voltage controlled by a CMFB
circuit. This amplifier CMFB works together with the CMFB at the
input stage to prevent common-mode current from flowing into
the transimpedance stage. The differential photocurrent input to the
transimpedance stage is is1 þ (is2=2). Both photocurrents positively
contribute to the TIA output and thus improve overall responsivity.
The last stage is the feedback DC rejection stage. In the feedback
loop, a capacitor Cf and operational transconductance amplifier (OTA)
work together as a differential integrator. The OTA has a fully
differential folded-cascaded structure, similar to that reported [6]. An
integrator in the negative feedback circuit amplifies and thus suppresses
the low frequency signal. However, within the signal band
(95–105 kHz) the feedback loop gain is extremely weak and signals
are not affected. Specifically, as shown in Fig. 1, the DC photocurrents
ID1 and ID2 are shunted to transistors M1 and M2 instead of the
transimpedance stage. In the steady state, the current flow is
IB þ ID1 þ (ID2=2) for M1 and IB ꢀ ID1 ꢀ (ID2=2) for M2. Therefore,
the feedback loop acts as a closed loop highpass filter (HPF). The cutoff
frequency of the HPF is changed by adjusting an external resistor that
sets the OTA transconductance.
High-gain differential CMOS
transimpedance amplifier with on-chip
buried double junction photodiode
W. Xu, D.L. Mathine and J.K. Barton
An integrated fully differential CMOS transimpedance amplifier (TIA)
with buried double junction photodiode input is described. The TIA
features a variable high transimpedance gain (250 kO to 2.5 MO),
large DC photocurrent rejection capability (>55 dB) and low input
referred noise density at 100 kHz (2pA= Hz).
p
Introduction: The transimpedance amplifier (TIA) is widely used in
optical receiver circuits. The majority of CMOS TIA designs reported
in the literature are intended for high speed digital signal reception.
The TIA reported in this Letter is optimised for low noise analogue
optical signal detection, in a situation where a weak modulated optical
signal is superimposed on a large DC background. This type of signal
may be encountered for example in optical coherence tomography
(OCT) [1]. Specifically, our design is optimised to detect a 100 kHz
carrier frequency, 5 kHz bandwidth signal, and to reject an unwanted
DC component with 50 dB attenuation compared to the signal band
gain. Our TIA differs from other similar designs [2, 3] through the
unique combination of an on-chip buried double junction (BDJ)
photodiode, very high adjustable gain and attendant low noise.
Simulation and measurement: The BSIM3 level 49 transistor model
was used in HSPICE simulations of the TIA. Because an accurate
flicker noise model is not available, the simulated noise spectrum
includes thermal noise only.
Circuit description: A block diagram of the differential TIA is shown
in Fig. 1. The circuit has three main parts: input stage, transimpedance
stage and feedback DC rejection stage. The input stage includes a
BDJ [4] photodiode and associated circuitry. A cross-section of the
BDJ photodiode is shown in Fig. 2. A 60 by 60 mm Pþ-diffusion and
N-well junction forms the Pþ=N-well photodiode. The N-well and
P-substrate junction forms the P-sub=N-well photodiode. As shown in
The optical receiver (TIA and BDJ photodiode) was fabricated in a
1.5 mm process and supplied with ꢁ 3.5 V. In addition to the optical
receiver, the fabricated chip also contained an additional BDJ photo-
diode for responsivity testing at 847 nm. The measured responsivities
of the Pþ=N-well and P-sub=N-well photodiode were 0.036 and
0.186 A=W, respectively. The optical receiver frequency response was
measured within the frequency range 30–500 kHz using an optical
input signal. At each frequency the TIA gain was computed by dividing
the optical receiver gain by the overall BDJ photodiode responsivity.
The measured TIA frequency response is shown in Fig. 3, with the TIA
gain control voltage set to 1.6 V. The shape of the response and
high=low frequency cutoffs are as expected. The peak gain at
100 kHz is 1.1 MO. By varying the TIA gain control voltage from
3.5–1.35 V, gains of 250 kO and 2.5 MO were measured at 100 kHz.
Fig. 1, the photocurrent of the Pþ=N-well photodiode is is1 þ ID1
,
where is1 is AC signal and ID1 is DC background, similarly the
photocurrent of the P-sub=N-well is is2 þ ID2. The common-mode
feedback (CMFB) circuit senses the common-mode voltage at the
input to the transimpedance stage and creates an amplified error signal
(relative to a 0 V reference) that controls two identical current
sources. The current sources then drive the common-mode voltage
to zero. In the steady state, each of the identical current sources has a
current of IB þ (Is2 þ ID2)=2, where IB is a constant bias current.
Transistors M3 and M4 are used to provide approximately 1.3 V
bias voltage for the Pþ=N-well photodiode.
1.2
V
dd
transimpedance
stage
input stage
1.0
i
+I
s2 D2
I
+
B
2
CMFB
Z
0.8
0.6
M3
i
+I
+
s1 D1
i
–
+
s2
2
i
+
s1
–
M4
i
+I
s2 D2
Z
V
ss
0.4
0.2
0
I
I
D2
2
D2
2
I
+I
+
I
–I
–
D1
B
D1
B
–
+
M1
M2
C
OTA
f
+
–
4
5
6
10
10
10
frequency, Hz
2I
B
V
feedback stage
ss
Fig. 3 Measured transimpedance amplifier frequency response
Fig. 1 Transimpedance amplifier block diagram
A dynamic signal analyser (Agilent 35670A) was used for noise and
DC rejection measurements. For noise measurement, the photodiode
input was blocked and the noise density at the TIA output was
measured. The TIA equivalent input current noise density was
computed by dividing the measured TIA output noise density by the
pp
V
pp
ss
nw
P+/N-well
nw
P+
N-well
P substrate
P-sub/N-well
measured transimpedance gain (1.1 MO). Fig. 4 shows the measured
noise densities. The measured value at 100 kHz is 2 pA= Hz, which is
p
about three times greater than the simulated thermal noise value at the
same frequency (0.6 pA= Hz). The measured noise density shows a 1=f
V
ss
p
Fig. 2 Structure of on-chip buried double junction photodiode
ELECTRONICS LETTERS 6th July 2006 Vol. 42 No. 14