Full text of DOI:10.1002/1527-2648(200107)3:7<461::AID-ADEM461>3.0.CO;2-W

Integration Challenges for
Low Dielectric Constant Materials
By Helmuth Treichel,* and Chevan Goonetilleke
The more advanced an integrated circuit becomes, the more stringent are the demands for certain prop-
erties of a dielectric or insulating material. In addition, it is essential that the layer maintains its spe-
cific electrical, physical and chemical properties after incorporation in the device structure and during
subsequent processing. Due to temperature budget constraints and the accelerated decrease of feature
sizes below 0.25 lm one can no longer rely on traditional choices but has to search for alternatives,
both for low and high permittivity replacements. In this article we survey currently used low dielectric
constant materials and future trends for microelectronic applications. Modern semiconductor circuit
interconnection techniques now focus on the integration of copper-based thin film metallization and
low dielectric constant (low-k) insulating thin films using a strategy known as damascene processing.
The objective of this approach is the optimization of information processing speed in the circuit by
minimizing resistive and capacitive delays resulting from the electrical field interactions between adja-
cent conductors.
1 Introduction
2 The Need for Copper and Low Dielectric
Constant (Low k) Material
As circuit geometry's shrink, the intrinsic circuit delay will
increase due to greater resistance in the metal interconnects,
and also capacitance effects from the interconnects. Strategies
to reduce these so-called parasitic effects include incorporat-
ing metals with lower resistivity and higher electromigration
resistance values, such as copper, and providing electrical
isolation with insulating materials with low dielectric con-
stants.[2] Incorporating low-K dielectric materials into viable
sub-micron fabrication schemes will necessitate, among other
things, the development of robust chemical mechanical pol-
ishing (CMP) and cleaning processes (dry or wet) for these
materials.[3,4] The properties of a polymer depend strongly on
the curing process, which, for example, can effect the cross-
linking, and to some extent the nature of the functional
groups within the polymer.[5] Thus, the curing process typi-
cally plays a significant role in determining the chemical and
mechanical characteristics of the low dielectric constant mate-
rial.[6] The properties of a polymer depend upon its primary
and secondary and tertiary structures, too. The properties of
a dielectric film composed of organic polymer also ultimately
depend upon the same factors. However, the actual film that
one achieves on the wafer has the additional dependence on
solvent types and the cure process used. The cure is driven
by the polymer solution and the desired properties of the
final film.
Scaling down the feature sizes in microelectronic circuits
has shown efficient in improving circuit performance and
increasing yield at lower cost per function on chip. Circuit
speed increases are primarily due to reduction in transistor
gate lengths, resulting in faster transistor switching times. As
dimensions are scaled to the sub-micron range the signal
runtime delays caused by the higher RC product of the metal-
lization may overcome the benefits of a decreased gate length.
Based on a typical CMOS inverter circuit scheme Bothra
et.al.[7] derived an analytical expression for the dependence of
signal rise time on the technological parameters. Their main
result is that a higher interconnect performance or less switch-
ing delay is to be achieved by introducing materials with
higher electro migration resistance for the interconnects and
by the use of lower dielectric constant insulators (see Fig. 1).
[*] H. Treichel, Ch. Goonetilleke
Novellus Systems
Surface Integrity Group
2730 Junction Avenue
San Jose, CA 95134 (USA)
E-mail: helmuth.treichel@novellus.com
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Treichel, Goonetilleke/Integration Challenges for Low Dielectric Constant Materials
Fig. 1. Summary timeline of the materials and processes anticipated in future generation interconnect structures.
Higher EM resistance allows one to pump more current
per unit cross section, which also helps performance. The
higher EM resistance of Cu allows one to use lower cross sec-
tion metal lines which reduces the capacitance.
the velocities of operation and corresponding power con-
sumption. The RC constant is a function of the resistivity of
the metal used (normally AlSiCu) and the capacitance of the
combined metal/intermetal dielectric structure (see Fig. 3).
The damascene approach to interconnect formation is
shown in Figure 2. In this method, the low-k material is
deposited and then patterned to remove the regions wherein
the metal conductors are formed. The copper and barrier
metal typically deposited after patterning using electroplat-
ing and sputtering processes, respectively.
Note, that we expect that any hard mask material is being
removed either during Cu/barrier CMP or is eliminated in
future interconnect schemes altogether.
For a quarter micron technology at a median interconnects
length of 1000 lm, the authors predict a switching delay
improvement of a factor of two for a material with k= 2 com-
pared to the usage of SiO2 as insulator. In ultra large-scale
integrated circuits, where critical dimensions continue to
shrink into the deep sub-micron range, the RC constant
becomes an increasingly dominant factor in governing both
3 General Requirements for Low-k
(i) Low dielectric constant (preferably isotropic[8]); an
anisotropic k would be acceptable if it was low in all directions
and lowest horizontally. (ii) Low water absorption. (iii) Good
chemical and thermal stability, high glass transition tempera-
ture TG9. (iv) High gap-fill and planarization capability, as
required for the process. (v) Low film stress. (vi) Good electrical
properties (low dielectric loss, positive effect to the hot carrier
degradation effect, low shift of the threshold-voltage caused by
mobile charges, low leakage current, low power consumption)
It cannot be sufficiently stressed that the electrical proper-
ties of insulator films are a function of the way they are
Fig. 3. Parasitic Capacitor Formation as Function of Design Rule (Source: Fujitsu).
Fig. 2. Copper damascene interconnect structure scheme.
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Treichel, Goonetilleke/Integration Challenges for Low Dielectric Constant Materials
deposited or grown, including polymer structure or precur-
sor structure. Depending on the conditions employed, vary-
ing degrees of structural perfection, electronic defect concen-
tration, dislocations, void or porosity content, density,
morphology, chemical composition, stoichiometry, electron
trap densities, etc. result with dramatic property implications.
Insulators are particularly prone to those effects. Stress, incor-
porated or adsorbed impurities are some other factors that
can alter the character of the insulating films. They are also
susceptible to aging, water absorption, atmospheric oxida-
tion, and low-temperature solid-state reactions.[9]
Fig. 5). Due to the inherent properties of spun-on materials
these materials show global planarization, however, there may
be problems with gap filling of very small features. Further
concerns are film shrinkage, cracking during drying, and the
content of adsorbed water. Integration into microelectronic de-
vices requires that the pore size must be significantly smaller
than the minimum feature size, and the pore size distribution
must be tight to maintain a good uniformity of the electrical
and mechanical properties of the films. First data on process
integration of xerogels into ILD modules show a promising
potential[11] (see Fig. 6). Integration issues, though, like the
elimination of extra layers (e.g., barriers, hard masks) will have
to be resolved to take full advantage of the porous materials
Further low dielectric constant materials are described
elsewhere.[12]
4 Low-k Materials
In the last few years, low-k materials deposition by CVD
has become increasingly more popular. Recent surveys of the
literature show a significant increase of publications related
to this technology. Deposition can be accomplished by ther-
mal or plasma assisted reactions. The reaction conditions for
CVD of low-k materials are different from common CVD and
must be developed and optimized for each material. How-
ever, films with excellent uniformity and conformality can be
synthesized even on large area substrates (only in the case of
thermal CVD. HDP provide gap file, but not conformality.
PECVD low-k films are very non-conformal.) Further investi-
gation and integration is in some cases limited as for the most
promising polymers the source materials are not commer-
cially available and difficult to synthesize. Enhancement of
the deposition rates is also necessary in most cases.
The low-k field has been narrowed considerably over the
last two years or so and now only a few strong candidates
remain. Organosilicate glass films (OSG) have an as-depos-
ited dielectric constant of about 2.9 and are relatively hard
(compared to other low-k films) at 1.5 GPa (Nano Indenta-
tion). Fabrications of interconnect structures in OSG required
development of certain unit processes. Putting these pro-
cesses together, electrically testable features with three levels
of Cu wiring in OSG were built (see Fig. 4).
5 Challenges in Stripping Photo Resist in the
Presence of Low-k
Traditionally photo resist stripping was performed with
high temperature (270 ꢀC), applying oxygen microwave plasma
processes. The silicon dioxide dielectric material, a 100 % inor-
ganic material did not react with the oxygen radicals generated
by microwave plasma. Thus, the photo resist could be removed
with no damage to the silicon dioxide dielectric. The low-k
dielectric materials on the other hand, have an organic compo-
nent in the structure. The oxygen generated from the traditional
plasma strip processes is not able to differentiate the carbon in
the photo resist from carbon in the low-k film. Therefore, apply-
ing an oxygen plasma process will deplete the carbon. This will
result in an undesirable increase in the dielectric constant often
referred to as ªdielectric damageº. To address this problem of
dielectric damage, non-oxygen based plasma strip processes
have been in development. These approaches focus on using
low temperature, (30-60 ꢀC) hydrogen-based plasmas to strip
the photo resist. Hydrogen and ammonia plasmas have
emerged as the main contenders. The photo resist strip rates
with the hydrogen-based gases are a fraction (about 1/10th) of
the rate obtained with oxygen-based plasmas. The low rate has
not been a big concern, yet, since the photo resist to be removed
in the low-k integration scheme is much less (about 1/3rd) than
the traditional silicon dioxide based schemes. The hydrogen
species in the plasma has also a milder effect on the dielectric
constant and thus, has evolved as a better compromise.
The material that looks most promising to combine the high
thermal stability of silica with the lowest achievable dielectric
constant is likely to be nanoporous or mesoporous silica. This
material consists of a silica network containing a high fraction
of small pores with diameters in the nanometer range[10] (see
6 Summary
The progress in silicon technology, the decreasing feature
sizes connected with a simultaneously increasing integration
density has raised a vital interest in low dielectric constant mate-
rials. High quality films can be obtained either by CVD or spin-
on techniques. An opportunity exists to determine and increase
the performance of the next generation dielectrics by joining the
combined expertise of an equipment manufacturer's business
unit with experts in the fields of multilevel interconnects and
Fig. 4. Three levels of Cu interconnect in OSG/SiC:H (WCVD contact plugs).
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Treichel, Goonetilleke/Integration Challenges for Low Dielectric Constant Materials
Fig. 5. Mesoporous material with homogeneous pore
size distribution.
Fig. 6. Cu/Xerogel Integration (Sources: IBM and
TI)
polymer chemistry as well as the production sites dedicated to
next generation device development and production.
[4] K. Wijekoon, S. Mishra, S. Tsai, K. Puntambekar, M. Chan-
drachood, F. Redeker, R. Tolles, B. Sun, L. Chen, T. Pan,
P. Li, S. Nanjangud, G. Amico, J. Hawkins, T. Myers,
R. Kistler, V. Brusic, S. Wang, I. Cherian, L. Knowles,
C. Schmidt, Ch. Baker, IEEE/SEMI Adv. Semicond. Man-
uf. Conf., 1998.
7 Outlook
The use of low-k materials represents a major shift in semi-
conductor device interconnect fabrication. The effective use
of subsequent processing will play a key role in successful
implementation of these films. While conventional oxides
and nitrides show few integration issues related to chemical
interactions, many of the new low-k dielectric materials gen-
erally show higher reactivity. Backend-of-the-line (BEOL)
process temperatures up to 450 ꢀC dictate the thermal stabil-
ity requirements of intermetal dielectrics. This largely elimi-
nates the majority of organic polymers from consideration.
As the BEOL process temperatures become lower, the situa-
tion will relax somewhat.
[5] H. S. Nalwa, M. Suzuki, A. Takahashi, A. Kageyama,
Appl. Phys. Letters, 1998, 72-11, 1311.
[6] G. W. Meyer, D. L. Dunson, J. E. McGrath, Abstracts of
papers, 6th Int. Conf. Polyimides and other Low K Dielectrics,
McAffee, New Jersey, 1997, 37.
[7] S. Bothra, I. Harvey, M. Weling, Proc. 14th Int. VLSI Mul-
tilevel Interconnect. Conf., 1997, 134.
[8] T. M. Lu, S. P. Murarka, T. S. Kuan, C. H. Ting, Mat.
Res. Soc. Symp., 1996, 381, 239.
[9] G. Maier, J. M. Schneider, R. Hecht, Mat. Res. Soc. Symp.
Proc., 1996, 443, 59.
[10] C. Jin, S. List, W. W. Lee, C. Lee, J. D. Luttmer, R. Have-
mann, D. Smith, T. Ramos, A. Maskara, Abstr. Adv. Met.
Interconn. Systems ULSI Appl., 1996.
[11] C. Jin, J. D. Luttner, D. M. Smith, T. A. Ramos, Mat. Res.
Soc. Bulletin, 1997, 39.
[12] H. Treichel, B. Withers, G. Ruhl, P. Ansmann, R. Wuerl,
Ch. Mueller, M. Dietlmeier, G. Maier, Handbook of Low
and High Dielectric Constant Materials and Their Applica-
tions, (Ed. H. S. Nalwa)., Academic Press, 1999, 1, 1.
[13] C. J. Brinker, M. T. Anderson, R. Ganguli, Y. Lu, Pro-
cess to Form Mesostructured Films, U.S. Patent
5,858,457, 1999.
[1] D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote,
C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff,
A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz,
L. Su, S. Luce, and J. Slattery, Full Copper Wiring in a
Sub-0.25 lm CMOS ULSI Technology, in Proc. IEEE
IEDM, 1997, pp. 773±776.
[2] P. Singer, Semicond. Int., 1996, 60.
[3] J. Neirynck, S. Murarka, R. Gutmann, Investigation of the
Chemical Mechanical Polishing of Polymer Films for ILD
Applications, MRS Proc., 1996, 381.
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