High ON/OFF ratio and multimode transport in silicon nanochains field effect transistors

Article abstract of DOI:10.1063/1.3694046

We have observed multimode transport and high ON/OFF ratio in silicon nanochain devices. Silicon nanochains grown by thermal evaporation of SiO solid sources consisted of chains of silicon nanocrystals ～10 nm in diameter, separated by SiO₂ regi

Full text of DOI:10.1063/1.3694046

High ON/OFF ratio and multimode transport in silicon nanochains field effect
transistors
M. A. Rafiq, K. Masubuchi, Z. A. K. Durrani, A. Colli, H. Mizuta, W. I. Milne, and S. Oda
Citation: Applied Physics Letters 100, 113108 (2012); doi: 10.1063/1.3694046
View online: http://dx.doi.org/10.1063/1.3694046
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APPLIED PHYSICS LETTERS 100, 113108 (2012)
High ON/OFF ratio and multimode transport in silicon nanochains field effect
transistors
1
,2,3,a)
1
K. Masubuchi, Z. A. K. Durrani, A. Colli, H. Mizuta, W. I. Milne,
2,4
5
2,6
2,7
M. A. Rafiq,1
and S. Oda
,2
1
Quantum Nanoelectronics Research Centre, Tokyo Institute of Technology, O-Okayama, Meguro-ku,
Tokyo 152-8552, Japan
SORST JST, Japan
Micro and Nano Devices Group, Department of Metallurgy and Materials Engineering, Pakistan Institute
of Engineering and Applied Sciences, Islamabad, Pakistan
Department of Electrical and Electronic Engineering, Imperial College London, South Kensington Campus,
2
3
4
London SW7 2AZ, United Kingdom
Nokia Research Centre C/O Nanoscience Centre, Cambridge CB30FF, United Kingdom
5
6
Nanoscale Systems Integration Group, School of Electronics and Computer Science, University
of Southampton, Southampton SO171BJ, United Kingdom
7
Department of Engineering, University of Cambridge, 9 J. J. Thomson Avenue, Cambridge CB3 0FA, United
Kingdom
(Received 31 January 2012; accepted 27 February 2012; published online 14 March 2012)
We have observed multimode transport and high ON/OFF ratio in silicon nanochain devices.
Silicon nanochains grown by thermal evaporation of SiO solid sources consisted of chains of
silicon nanocrystals ꢀ10 nm in diameter, separated by SiO regions. The devices were fabricated
2
using electron beam lithography on SiO thermally grown on silicon substrate. These devices
2
4
exhibited high ON/OFF current ratio up to 10 . The inverse subthreshold slope as small as
ꢀ
500 mV/decade was observed in these devices. Therefore, we believe silicon nanochains hold
great potential to be used in field effect transistors. VC 2012 American Institute of Physics.
http://dx.doi.org/10.1063/1.3694046]
[
One-dimensional nanostructures are attractive compo-
nents of future nanoelectronic devices such as field effect
use of silicon nanochains as functional components of field
effect transistors.
1–11
transistors (FETs).
For this reason, semiconductor nano-
To explore the possibility of use of silicon nanochains in
field effect transistor, we investigate electron transport in
multiple silicon nanochain devices. We fabricate back gated
devices, where multiple nanochains were present as channel
between source and drain contacts. The silicon nanochains
wires and carbon nanotubes have been used as channel mate-
rial in FETs. Cui et al. studied high performance FETs based
on silicon nanowires prepared by nanocluster-mediated
1
growth method. More recently, silicon nanowires grown by
Au-catalyzed vapor-transport method have been utilized to
20
were prepared by thermal evaporation of silicon monoxide.
The silicon nanochains consisted of a chain of SiNCs
2
fabricate top-gated FETs. Heinze et al. demonstrated opera-
tion of carbon nanotube transistors as Schottky barrier tran-
ꢀ10 nm in diameter separated and covered by SiO . Clear in-
2
3
sistors. ZnO nanowires and graphene have also been used in
dication of multimode transport during electrical character-
isation of silicon nanochain devices was observed. These
devices exhibited subthreshold slope as small as ꢀ500 mV/
5
,12
fabrication of FETs.
4
The device concepts based on band
to band tunnelling have also been demonstrated in silicon
5
,6
4
and InAs nanowire FETs. However, silicon based one-
dimensional nanostructures are of considerable interest due
to their compatibility with present industry. In view of this,
we investigate possibility of silicon nanochains to be used in
FETs. Silicon nanochain is a unique necklace like structure
where a nanowire takes the form of silicon nanocrystals
decade. High ON/OFF current ratio ꢀ10 was also observed
in these devices. The characteristics of the silicon nanochain
FETs can be improved by reducing the gate oxide thickness
and doping the nanochains.
The silicon nanochains were synthesised by thermal
evaporation of 99.99% pure silicon monoxide powder, at
1
3–18
ꢁ
(
SiNCs) separated and covered by SiO2.
chains have attracted some attention recently.
et al. reported tunnelling electron transport in silicon nano-
Silicon nano-
1400 C in a quartz tube furnace. Argon gas was used to carry
the vapour through the tube. Silicon nanochains were synthes-
1
3–18
Kohno
ꢁ
ꢁ
ised in a cooler part of the furnace at 900 C–950 C, and the
nanochains were undoped. In addition, nanowires were also
present in the grown samples. Depending on the growth con-
ditions, 50%–90% of the final product takes the form of sili-
con nanochains. The nanochains may be considered as chains
13
chains during in situ scanning electron microscopy. Tang
et al. investigated the microstructure and field emission prop-
1
9
erties of boron doped silicon nanochains. It has also been
demonstrated that silicon nanochains have great potential to
fabricate room and low temperature single electron
of SiNCs, separated by SiO regions. Figure 1(a) shows a
2
16–18
transistors.
However, there are no studies on potential
transmission electron micrograph of a silicon nanochain. The
SiNC diameter varies from <10nm to ꢀ30 nm, and the sepa-
ration varies from ꢀ15nm to 40nm. SiNC is covered by a
a)
Electronic mail: fac221@pieas.edu.pk.
thin SiO layer, ꢀ1 nm–3 nm thick. The separation between
2
0003-6951/2012/100(11)/113108/4/$30.00
100, 113108-1
VC 2012 American Institute of Physics
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113108-2
Rafiq et al.
Appl. Phys. Lett. 100, 113108 (2012)
contacts were evaporated on to the silicon nanochains, after
wet etching of the SiO layer around the silicon nanochains
in the contact regions.
2
Figure 1(c) shows top view of a silicon nanochain de-
vice, respectively. Figure 1(d) shows a schematic diagram of
the nanochain device. The I -V characteristics of the devi-
D
DS
ꢃ6
ces were then measured in vacuum (ꢀ10 mBar) using a
needle prober (BCT-43MDC, Nagase & Co. Ltd.) and an
Agilent 4156C parameter analyser. The source-drain separa-
tion was ꢀ350 nm and few silicon nanochains were present
between source and drain contacts in this device (Fig. 1(c)).
Figure 2(a) plots the room temperature output curves
(
ID-VDS) for device A at VGS ¼ ꢃ10 V, ꢃ5 V, 0 V, and þ5 V.
FIG. 1. (a) Transmission electron micrograph of Si nanochains, prepared by
thermal evaporation of SiO. The image is slightly under-focused to empha-
size diameter variations. A JEOL 200CX transmission electron microscope
was used. (b) Scanning electron micrograph of a Si nanochain deposited on
2
SiO . (c) Scanning electron micrograph of a Si nanochain device. (d) Sche-
matic of a Si nanochain device.
the SiNCs varies from approximately the diameter of the
SiNCs, to well below this value. Figure 1(b) shows a scanning
electron micrograph of a silicon nanochain deposited on SiO2.
The silicon nanochain devices were fabricated by defin-
ing aluminium contacts to silicon nanochains, using
electron-beam (e-beam) lithography in poly methyl methac-
rylate resist. The devices were defined on silicon substrate
covered with a ꢀ200 nm thick thermally grown SiO . The
2
1
9
3
silicon was doped n-type to a concentration of 1 ꢂ 10 /cm
and it formed a global back-gate. Initially, an array of Cr/Au
alignment marks was fabricated by e-beam lithography on
the SiO layer. The array of alignment marks was used for
2
alignment purpose during successive lithography steps.
Next, the surface of the top SiO layer was treated with hex-
2
amethyldisilizane vapour treatment to improve the adhesion
between nanochains and SiO . 0.1 mg of silicon nanochains
2
were then dissolved in 3 ml isopropyl alcohol (IPA) using ul-
trasonic tip agitation for 5 min. The silicon nanochains were
then spun onto the sample at 5000 rpm. Finally, aluminium
FIG. 2. (a) I
at 300 K. (b) Log-linear plot of I
-VGS characteristics of a Si nanowire device (device “B”) at 300 K.
D
-VDS characteristics of a Si nanochain device (device “A”)
D
-VGS characteristics of device “A.” (c)
I
D
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113108-3
Rafiq et al.
Appl. Phys. Lett. 100, 113108 (2012)
The curves are nonlinear indicating that the contacts between
nanochains and metal leads are not ohmic, but rather a
2
1
Schottky barrier is present. Typical total device resistance
in the ON state is ꢀ25 GX. The high device resistance is
expected due to undoped nature of nanochains. We note,
however, that the output curves are non-symmetric indicat-
ing that contacts are in general nonequivalent. A wide distri-
bution of contact resistances may exist for a single
fabrication process, leading to a situation where only a few
nanochains are dominating the electrical transport for an
individual device.
Figure 2(b) shows the transfer characteristics of the
same device A. The gate leakage I remains within the noise
G
level, <0.1 pA (not shown). The values of I , I , and I con-
D
S
G
firm that the current flows through the silicon nanochains
and not via the gate. I is low in value because of the small
D
size and undoped nature of the SiNCs. In this device, strong
dependence of I on V is observed. I increases as the V
GS
D
GS
D
is decreased and I is blocked when VGS is increased. This
D
indicates that the nanochain transistor behaves as p-type
transistor. The behaviour is similar to previous reports,
where it has been demonstrated that undoped nanowire FETs
2
0,22
usually behave as p-type transistor.
The nanochain FETs
exhibits ambipolar behaviour. The current due to electrons,
however, always shows a lower subthreshold slope compared
to holes as can be seen from Figure 2(b). All nanochain devi-
ces exhibited similar characteristics. The transconductance
ꢀ
0.1 pS was determined for this device. The value is low
because of undoped nature of the nanochains. The value can
be improved by doping the nanochains. Further, reduction in
23
gate oxide will also improve the transconductance value.
The inverse subthreshold slopes S of the device A at
VDS ¼ ꢃ6, ꢃ4, and ꢃ2 V are 500 mV/decade, 500 mV/dec-
ade, and 1000 mV/decade, respectively, was extracted from
Figure 2(b). The obtained values of the S are not close to
ideal value of S at room temperature, i.e., 60 mV/decade.
However, these values are better than the values of S
FIG. 3. (a) Linear-linear plot of I
D
-VGS characteristics of device “A” at
VDS ¼ ꢃ2 V and (b) device “C” at VDS ¼ ꢃ20 V showing step-like behaviour.
current through one subband saturates when current level
reaches the current level associated with the quantized con-
5
obtained for silicon nanowire tunnelling FETs. However,
the values of S can be further reduced by decreasing the gate
2
ductance 4e /h. In our nanochains, the silicon nanocrysals
forming the nanochain are of very small diameter (large sep-
aration between subbands) and, therefore, it is expected that
multimode transport may be visible in nanochains at room
temperature. Many silicon nanochain devices exhibited such
step-like behaviour. Figure 3(b) shows the multimode trans-
port in another silicon nnaochain device C.
24
oxide thickness. In our devices, we used gate oxide thick-
ness ꢀ200 nm. Therefore, there is great potential to improve
the value of S in our devices by reducing the gate oxide
thickness below 50 nm. The ON/OFF current ratio of this de-
2
4
vice increases from 10 at V ¼ ꢃ2 V to 10 at V ¼ ꢃ4 V
DS
DS
4
and it remains 10 at V ¼ ꢃ6 V. Figure 2(c) shows the
DS
In conclusion, we have observed large ON/OFF ratio
and multimode transport in silicon nanochain FETs. Si nano-
chains were grown by thermal evaporation of SiO solid sour-
ces. The nanochains consisted of chains of SiNCs ꢀ10 nm in
transfer characteristics of a device B with source drain sepa-
ration ꢀ500 nm. The inverse subthreshold slopes S of the de-
vice at V ¼ ꢃ6, ꢃ4 volts is ꢀ600 mV/decade. The ON/
DS
3
OFF current ratio of this device is 10 .
diameter, separated by SiO regions. High ON/OFF current
2
Figure 3(a) shows the presence of step-like features in
the I -V characteristics of the device A. This may be due
4
ratio up to 10 has been observed in these devices. Further,
D
GS
the inverse subthreshold slope S ꢀ500 mV/decade is
observed in these devices. ON/OFF current ratio and S can
be improved by reducing the gate oxide thickness and doping
the nanochains. Therefore, we believe silicon nanochains
hold great potential to be used in fabricating FETs.
to stepwise increase of current carrying 1D modes in the
nanochains when VGS is increased, i.e., made more negative
in present case (p-type FET). Appenzeller et al. observed
25
similar step-like behaviour in carbon nanotube FETs. They
argued that such steps can be made visible by introducing
scattering sites such as doping the nanotube. Here, in present
case, the scattering sites may be present at the silicon nano-
The work was supported by Grant-in-Aid for scientific
research from the Japan Society for Promotion of Science
(JSPS) Nos. 22246040 and 19-07107. M.A.R. would like to
acknowledge the support from JSPS.
crystal/SiO interface. They further argued that multimode
2
transport can appear for small diameter nanotubes, where the
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