Polycrystalline silicon/CoSi2 Schottky diode with integrated SiO2 antifuse: A nonvolatile memory cell

Article abstract of DOI:10.1063/1.1581364

The development of a low-cost, field-programmable memory cell device based on CoSi₂/polysilicon Schottky diodes with integrated SiO₂ antifuses was discussed. An SiO₂ antifuse thin film was also grown in between the polysilicon and CoSi₂. The ability to grow thin, high quality SiO₂ films directly on CoSi₂ allowed cells to be formed using a polysilicon deposition doped with a single dopant type.

Full text of DOI:10.1063/1.1581364

Polycrystalline silicon/CoSi 2 Schottky diode with integrated SiO 2 antifuse: a
nonvolatile memory cell
S. B. Herner, M. Mahajani, M. Konevecki, E. Kuang, S. Radigan, and S. V. Dunton
Citation: Applied Physics Letters 82, 4163 (2003); doi: 10.1063/1.1581364
View online: http://dx.doi.org/10.1063/1.1581364
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/82/23?ver=pdfcov
Published by the AIP Publishing
Articles you may be interested in
Controlled fabrication of Si nanocrystal delta-layers in thin SiO2 layers by plasma immersion ion implantation for
nonvolatile memories
Appl. Phys. Lett. 103, 253118 (2013); 10.1063/1.4848780
Formation of iridium nanocrystals with highly thermal stability for the applications of nonvolatile memory device
with excellent trapping ability
Appl. Phys. Lett. 97, 143507 (2010); 10.1063/1.3498049
Nonvolatile memory with switching interfacial polar structures of nano Si-in-mesoporous silica
Appl. Phys. Lett. 95, 143501 (2009); 10.1063/1.3240888
Application of plasma enhanced chemical vapor deposition silicon oxynitride layers in nonvolatile semiconductor
memory devices
J. Vac. Sci. Technol. B 27, 494 (2009); 10.1116/1.3054353
Nonvolatile low-temperature polycrystalline silicon thin-film-transistor memory devices with oxide-nitride-oxide
stacks
Appl. Phys. Lett. 90, 182115 (2007); 10.1063/1.2736293
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 158.42.28.33
On: Wed, 26 Nov 2014 11:08:54

APPLIED PHYSICS LETTERS
VOLUME 82, NUMBER 23
9 JUNE 2003
Polycrystalline siliconÕCoSi Schottky diode with integrated SiO antifuse:
2
2
a nonvolatile memory cell
S. B. Herner,a) M. Mahajani, M. Konevecki, E. Kuang, S. Radigan, and S. V. Dunton
Matrix Semiconductor, Santa Clara, California 95054
͑
Received 17 January 2003; accepted 8 April 2003͒
A Schottky diode consisting of doped polycrystalline silicon ͑polysilicon͒ and CoSi films is
2
described. When an SiO antifuse thin film is grown in between the polysilicon and CoSi , the film
2
2
stack can function as a nonvolatile one-time programmable memory cell. The cell is programmed
when the SiO that insulates the doped polysilicon from the CoSi is broken down by applying a
2
2
large biasing field, and unprogrammed when the antifuse is not broken down. By taking advantage
of the ability to grow SiO directly on CoSi , the entire device can made with only two masking
2
2
steps and relatively simple tool set, while achieving high density. © 2003 American Institute of
Physics. ͓DOI: 10.1063/1.1581364͔
ϩ
We describe a nonvolatile cell for one-time field-
programmable read-only memories. The device described in
this paper is a Schottky diode made from in situ doped-
phous n -doped silicon film was patterned using standard
lithographic techniques, and then etched to produce 0.22-
␮m-wide lines. After silicon was etched and photoresist was
polycrystalline silicon ͑polysilicon͒ and CoSi . A thin SiO2
stripped, high-density plasma CVD SiO was deposited to
2
2
antifuse is grown on top of the CoSi , followed by doped
isolate the silicon lines. The wafers were chemomechanically
2
polysilicon deposition and then another film of CoSi . The
polished to remove SiO from the top of the silicon lines,
2
2
CoSi film forms the interconnection to the cell. A diode is
producing a planarized surface ͓Fig. 1͑a͔͒.
2
formed when enough voltage is applied across the SiO film
A selective process was used to form CoSi2 on top of the
silicon, forming the bit lines. After an HF dip to clean the
silicon of any native oxide on the silicon lines, cobalt and
titanium were sputtered in a cluster tool. Wafers were rapid
thermally annealed ͑RTA͒ to form CoSix . Unreacted Co
ϩTi were then removed by wet etching. A second RTA at
740 °C converted the remaining CoSix to CoSi2 . Resulting
CoSi2 was approximately 50 nm thick. Antifuses were grown
on the CoSi2 by oxidation in a RTA chamber using 5 liters of
oxygen gas ͑99.9999% purity͒ at various temperatures and
2
to break it down and create a metal–semiconductor junction.
Other forms of this device have been presented. De Graaf
et al. described a diode-programmable read-only memory
ϩ
Ϫ
cell based on n /p diodes using a combination of poly-
crystalline and single-crystal silicon with integrated
1
ϩ
Ϫ
antifuses. More recently, Crowley et al. described a p /n
diode cell based completely on polysilicon with integrated
2
SiO2 antifuse. By using polysilicon, the cells could be
stacked above the transistor drivers in single-crystal silicon,
and one another, reducing die size compared to single crystal
silicon-based cells. Both of the cells achieved a high density
with relatively few masking steps. However, both the cells
required n- and p-type doping of silicon, and placed the an-
tifuse in between two silicon films. The Schottky diode-
based cell described in this letter achieves the same high
density, but at lower cost with simplified fabrication. The cell
described here requires only one type of doped silicon, and
times ͓Fig. 1͑b͔͒. A second PH -doped silicon deposition was
3
then done, doping the first 100–300 nm to a concentration of
3
1
Ϫ3ϫ1017 phosphorus/cm , and the final 100–200 nm to a
2
0
3
concentration of 1.3ϫ10 phosphorus/cm . Steps were then
repeated to form a second set of silicon lines orthogonal to
the first, with SiO gap-fill and CoSi conductive lines on top
2
2
͑the word lines͒. The anneals crystallized the amorphous sili-
con and activated the dopants. Chemomechanical overpolish
of the gap-fill SiO on top of silicon was carefully controlled
the antifuse (SiO ) is grown directly on the interconnection
2
2
ϩ
to leave at least 10 nm of n -doped silicon on top of the
(
CoSi ) for the cell. By taking advantage of in situ doping of
2
second polysilicon lines ͓Figs. 1͑c͒ and 1͑d͔͒. This ensures
silicon to vary depth profile concentration instead of ion im-
plantation, process complexity is minimized. We describe de-
vice fabrication, breakdown properties of the antifuse related
to growth conditions, and cell operation.
an ohmic contact between the silicon and CoSi . Antifuses
2
were not grown on top of the second film of CoSi . Thick
2
oxide was then deposited by plasma-enhanced CVD, and
tungsten vias connected the second CoSi film to aluminum
Devices were fabricated on 200-mm oxide-coated silicon
wafers using 0.22-␮m lithography. Silicon was deposited
with a low-pressure chemical vapor deposition ͑CVD͒ fur-
nace operating at 400 mTorr, 540 °C, using helium-diluted
SiH and doped with PH ͑bal. He͒. The first silicon film was
2
pads on top of the thick oxide ͑‘‘top metal’’͒. A cross-
sectional transmission electron microscope ͑TEM͒ micro-
graph of four cells is shown in Fig. 2.
Single diodes were tested using an Agilent 4156C semi-
conductor parameter analyzer. Voltage was applied in
4
3
2
0
3
phosphorus-doped to a concentration of 1.3ϫ10 /cm , as
‘‘sweep’’ fashion, using a sweep rate of 3 V/s from 0 to ϩ10
measured by secondary ion mass spectrometry. The amor-
V, and then back to 0 V, and from 0 to Ϫ6.5 V and then back
to 0 V. TEM was used to measure SiO antifuse film thick-
2
a͒Electronic mail: brad@matrixsemi.com
ness. Areas of the TEM foil where the CoSi film is orthogo-
2
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 158.42.28.33
003-6951/2003/82(23)/4163/3/$20.00 4163 © 2003 American Institute of Physics
On: Wed, 26 Nov 2014 11:08:54
0

4164
Appl. Phys. Lett., Vol. 82, No. 23, 9 June 2003
Herner et al.
FIG. 2. Cross-sectional transmission electron micrograph, using bright-field
conditions, of four bit lines and a word line ͑the location of the antifuse film,
AF, is indicated, but is too thin to be visible in this image͒.
form thickness over the CoSi , even as they transition over
2
CoSi grain boundaries ͑Fig. 3͒. Thickness uniformity of the
2
antifuse film is important to achieve uniform breakdown
voltage for all devices.
The rough interface between polysilicon and CoSi is
2
typical for this film stack. Silicide grain boundary grooving
occurs as a result of the reduction in surface and interfacial
5
energy during anneal at elevated temperature. Silicide grain
boundary grooving results in a rough CoSi surface on which
2
the SiO antifuse film is grown. The median breakdown volt-
2
age for the antifuses grown at 700 °C for 20 s was found to
be 5.7 V with a 1-sigma variation of 0.5 V for 20 cells tested.
The median breakdown voltage for the antifuses grown at
8
7
00 °C for 30 s was 8.5 V. We extract a breakdown field of
.6 ͑5.7͒ MV/cm for the oxides grown at 700 °C/20 s
͑
800 °C/30 s͒ on CoSi , compared with reported values
2
1
2.6–14.0 MV/cm for high-quality SiO grown on single-
2
6
crystal silicon. The relatively rough SiO /CoSi interface
2
2
shown in Fig. 3, compared to SiO grown on single-crystal
2
silicon undoubtedly leads to a greater density of defects at
the interface, particularly at CoSi2 grain boundaries. The
7
roughness increases the local electric field. Interface rough-
ness increases with increasing SiO2 growth temperature,
with silicide grain grooving occurring simultaneously. The
FIG. 1. Schematic flow of the process steps to make the memory cell. ͑a͒
bit-line ͑BL͒ formation: doped silicon lines with SiO insulation in between;
2
lower breakdown field of the SiO antifuse film grown at
͑
b͒ formation of CoSi and SiO antifuse on top on BLs; ͑c͒ word line ͑WL͒
2
2
2
formation: doped silicon lines orthogonal to the BLs underneath, with CoSi2
on top; and ͑d͒ plan view of the cells (Fϭfeature size).
800 °C compared to the one grown at 700 °C ͑Table I͒ is
consistent with higher local fields produced by a rougher
CoSi film.
2
A typical (I–V) curve for the memory cell is shown in
nal to the foil were selected for thickness measurement to
minimize error from the rough CoSi /poly-Si interface.
2
TABLE I. Properties of the SiO2 antifuse film with growth conditions
The breakdown voltage of the SiO film was found to
2
(
N/Aϭnot available͒.
correspond generally to the thickness of the oxide film, and
was not a strong function of the doping concentration or the
thickness of either the lightly or heavily doped polysilicon
films ͑Table I͒. Previous work has shown that oxides grown
on CoSi are stoichiometric SiO , although this has been
SiO2 growth
conditions
SiO thickness
by TEM ͑nm͒
Breakdown
voltage ͑V͒
Breakdown
field ͑MV/cm͒
2
͑
5-L O flow͒
2
670 °C/20 s
700 °C/20 s
N/A
5.0
5.7
N/A
N/A
8.5
N/A
7.6Ϯ0.5
N/A
N/A
5.7Ϯ0.2
2
2
3
7.5Ϯ0.5
8.2Ϯ0.5
9.0Ϯ0.5
15.0Ϯ0.5
confirmed only on much thicker SiO films ͑Ͼ 20 nm͒. The
2
7
7
00 °C/40 s
00 °C/120 s
only report of very thin oxides grown on CoSi could not
2
4
confirm that the films were stoichiometric SiO . Cross-
2
800 °C/30 s
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 158.42.28.33
sectional TEM imaging shows that the SiO films have uni-
2
On: Wed, 26 Nov 2014 11:08:54

Appl. Phys. Lett., Vol. 82, No. 23, 9 June 2003
Herner et al.
4165
Low reverse current ͑‘‘leakage’’͒ minimizes current loss and
prevents breakdown in nonselected bit lines. The ‘‘program-
ming’’ voltage ͑ϩ5.5 V in this example͒ of the cell is much
higher than the ‘‘read’’ voltage ͑ϩ3 V͒ to avoid conflicts
between programming and reading the device. The current
difference at ϩ3 V equivalent to six orders of magnitude
between a programmed cell and an unprogrammed cell pro-
vides the ability to ‘‘sense’’ individual programmed and un-
programmed cells within relatively large arrays of cells.
We have developed a low-cost, field-programmable
memory cell device based on CoSi /polysilicon Schottky di-
2
odes with integrated SiO antifuses. The ability to grow thin,
2
high-quality SiO films directly on CoSi allows cells to be
2
2
formed using a polysilicon deposition doped with a single
dopant type. The entire cell is formed with two masking
steps and a simple tool set. The cell is programmed when the
antifuse that insulates the doped polysilicon from the CoSi2
is broken down by applying a large biasing field, and unpro-
grammed when the antifuse is not broken down. The break-
FIG. 3. Transmission electron micrograph, using bright-field conditions, of
SiO film on CoSi . Oxide growth was done at 700 °C, 760 Torr, in 5 L of
O2 flow for 120 s. The SiO2 film has been ‘‘capped’’ with polysilicon to
provide better contrast.
2
2
Fig. 4. The selected cell has a high voltage applied to the bit
line while the word line is held at ground. The unselected bit
and word lines are biased in the opposite polarity. The large
increase in forward current at ϩ5.5 V is indicative of break-
down field of the SiO film was found to be 5.6–7.6 MV/cm
2
compared to 12.6–14.0 MV/cm for high-quality gate oxide
grown on single-crystal silicon. Cell performance is based on
a difference in current of over six orders of magnitude be-
tween a programmed and unprogrammed bit at ϩ3-V read
voltage.
down of the SiO film separating the CoSi on the bit line
2
2
Ϫ
and n -doped silicon film in the word line. To minimize
power consumption during device operation, high forward
current at low voltage is preferred during read of the cell.
We thank M. Cleeves and A. Walker for fruitful discus-
sions regarding this work.
1
C. de Graaf, P. H. Woerlee, C. M. Hart, H. Lifka, P. W. H. de Vreede, P. J.
M. Janssen, F. J. Sluijs, and G. M. Paulzen, Int. Elect. Dev. Mtg., 7.6.1
͑
1996͒.
2
3
M. Crowley, A. Al-Shamma, D. Bosch, M. Farmwald, L. Fasoli, A. Ilk-
bahar, M. Johnson, B. Kleveland, T. Lee, T.-Y. Liu, Q. Nguyen, R.
Scheuerlein, K. So, and T. Thorp, ISSCC Digest of Technical Papers,
2
003, p. 284.
M. Bartur and M. A. Nicolet, Appl. Phys. A: Mater. Sci. Process. 29, 69
1982͒; H. Jiang, C. S. Petersson, and M.-A. Nicolet, Thin Solid Films
40, 115 ͑1986͒; G. J. Huang and L. J. Chen, J. Appl. Phys. 76, 865
1994͒; I. D. Kaendler, O. H. Seeck, J.-P. Schlomka, M. Tolan, W. Press,
J. Stettner, L. Kappius, C. Dieker, and S. Mantl, J. Appl. Phys. 87, 133
2000͒.
͑
1
͑
͑
4
5
R. T. Tung, Appl. Phys. Lett. 72, 2538 ͑1998͒.
J. P. Gambino, E. G. Colgan, A. G. Domenicucci, and B. Cunnignham, J.
Electrochem. Soc. 145, 1384 ͑1998͒.
S. J. O’Shea, R. M. Atta, M. P. Murrell, and M. E. Welland, J. Vac. Sci.
Technol. B 13, 1945 ͑1995͒; M. Kimuri and H. Koyama, J. Appl. Phys. 85,
7671 ͑1999͒.
6
7
FIG. 4. Typical I–V curve for Schottky diode with SiO2 breakdown at
ϩ5.5-V forward bias voltage.
A. H. Carim and A. Bhattacharya, Appl. Phys. Lett. 46, 872 ͑1985͒.
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 158.42.28.33
On: Wed, 26 Nov 2014 11:08:54