Low-temperature solid phase epitaxy for integrating advanced source/drain metal-oxide-semiconductor structures

Article abstract of DOI:10.1063/1.3298354

We show that chemical vapor deposition using trisilane decomposition opens capabilities for the deposition of amorphous silicon on Si substrate at low temperature. Based on this behavior we developed a process including amorphous silicon deposition and crystallization. Transmission electron microscopy observations prove that solid phase epitaxy (SPE) occurs and produces monocrystalline layers, free of extended defects and compatible with complementary metal-oxide-semiconductor technology. We also show that during SPE films remain amorphous on oxidized areas while they transform into single crystal on Si. This process opens promising perspectives for the fabrication of advanced MOS structures.

Full text of DOI:10.1063/1.3298354

Low-temperature solid phase epitaxy for integrating advanced source/drain metal-
oxide-semiconductor structures
A. Gouyé, I. Berbezier, L. Favre, G. Amiard, M. Aouassa, Y. Campidelli, and A. Halimaoui
Citation: Applied Physics Letters 96, 063102 (2010); doi: 10.1063/1.3298354
View online: http://dx.doi.org/10.1063/1.3298354
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APPLIED PHYSICS LETTERS 96, 063102 ͑2010͒
Low-temperature solid phase epitaxy for integrating advanced source/drain
metal-oxide-semiconductor structures
1
,2,a͒
1
1
1
1
2
A. Gouyé,
I. Berbezier, L. Favre, G. Amiard, M. Aouassa, Y. Campidelli, and
2
A. Halimaoui
1
IM2NP UMR CNRS 6242, Campus de Saint Jérôme, Case 142, F-13397 Marseille Cedex 20, France
STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles Cedex, France
2
͑
Received 21 July 2009; accepted 22 December 2009; published online 9 February 2010͒
We show that chemical vapor deposition using trisilane decomposition opens capabilities for the
deposition of amorphous silicon on Si substrate at low temperature. Based on this behavior we
developed a process including amorphous silicon deposition and crystallization. Transmission
electron microscopy observations prove that solid phase epitaxy ͑SPE͒ occurs and produces
monocrystalline layers, free of extended defects and compatible with complementary
metal-oxide-semiconductor technology. We also show that during SPE films remain amorphous on
oxidized areas while they transform into single crystal on Si. This process opens promising
perspectives for the fabrication of advanced MOS structures. © 2010 American Institute of Physics.
͓
doi:10.1063/1.3298354͔
The objective of this work is to realize defect free, ultra-
highly doped single-crystal silicon layers using conventional
chemical vapor deposition ͑CVD͒ fully compatible with
complementary metal-oxide-semiconductor ͑CMOS͒ tech-
nology. For this purpose, we have developed a two-steps
process including amorphous silicon ͑a-Si͒ deposition and
solid phase epitaxy ͑SPE͒ at low temperature ͑LT͒. The crys-
tallization via SPE of a-Si layers has already been shown to
produce single-crystal ͑c-Si͒ layers that were doped at ex-
drogen ͑H ͒. It was kept constant during all the experiments
to maintain a total pressure of the reactor about 60 Torr. The
2
substrates used for experiments were ͑a͒ nominal ͑001͒Si
wafer; ͑b͒ 100 nm thick thermal SiO /͑001͒Si wafer; ͑c͒
2
patterned ͑001͒Si wafer with advanced MOS structures
͓polycrystalline Si gate, HTO coating, Si N spacers, and
3
4
shallow trench isolation ͑STI͔͒. The film thickness was de-
termined either by weight measurements or by spectroscopic
ellipsometry. Tapping mode atomic force microscopy ͑AFM͒
images were analyzed to determine the surface roughness
and the morphology of the layers ͑Digital Instruments
DI3100 NanoScope III͒. The boron doping depth profiles of
the layers were determined by SIMS using a CAMECA IMS
5F spectrometer. Microstructural and chemical analyses of
the layers were obtained by cross-section and plane view
transmission electron microscopy ͑TEM͒ observations. TEM
experiments were performed on a 200 kV JEOL 2010 FEG
equipped with dispersive energy spectroscopy and elastic en-
ergy loss spectrometry.
1
–3
tremely high levels. This process was used for the forma-
tion of source and drain ͑S/D͒ extensions where shallow and
highly activated junctions are needed. In the latter work,
amorphous layers were obtained by implantation of heavy
species ͑such as Ge͒ which is well known to create end of
4
range crystal defects that are detrimental for junction leak-
age.
The main advantages of the process developed here are
the low thermal budget, the full compatibility with CMOS
technology and the ability to produce in a single run both
monocrystalline and amorphous Si on the different surface
phases of the substrate. In this approach, two main critical
and challenging steps should be addressed: for a start the
deposition of a fully amorphous material. Since the layer has
to be totally free of any crystal grain or nanocrystal to avoid
the formation of a polycrystalline layer during the subse-
quent SPE step. The second challenge is the formation dur-
ing the SPE step of single c-Si totally free of defects and
with ultrahigh concentration of fully activated dopants.
Si deposition was performed by conventional CVD us-
®
5
ing Silcore . Kinetics of growth using trisilane and silane
are compared on Fig. 1 for identical incoming silicon atomic
In this work, the CVD of a-Si on ͑001͒Si and on SiO is
2
first presented. In the second part we report the LT-SPE ki-
netics. In the third section, the two-steps ͑CVD and crystal-
lization͒ process is integrated in CMOS technology for the
fabrication of raised S/D structures.
®
Thin films were grown in an industrial ASM Epsilon
reduced pressure CVD reactor, on 200 mm diameter wafers.
The precursor used for Si deposition is trisilane ͑Si H ,
3
8
®
Silcore ͒. For doping ͑p-type͒ of the films we used diborane
B H ͒. For all experiments, the carrier gas was purified hy-
2 6
͑
FIG. 1. ͑Color online͒ The growth rate of Si layers on ͑001͒Si and
SiO /͑001͒Si using Si H ͑triangles͒ and SiH4 ͑squares͒, in equivalent Si
2
3
8
a͒Electronic addresses: adrien.gouye@im2np.fr.
atomic flow, as a function of the growth temperature.
0
003-6951/2010/96͑6͒/063102/3/$30.00
96, 063102-1
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© 2010 American Institute of Physics
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063102-2
Gouyé et al.
Appl. Phys. Lett. 96, 063102 ͑2010͒
FIG. 3. TEM cross-section images of: ͑a͒ the film deposited at 400 °C on
͑
001͒Si. The inset reproduces the SAD pattern typical of the amorphous
phase ͑diffuse ring and total absence of spots͒; ͑b͒ the thin c-Si layer which
evidences ͑111͒ facets at the a/c interface; ͑c͒ the film after total crystalli-
zation by in situ SPE at 500 °C during 600 s. The inset reproduces the
corresponding SAD pattern which exhibits only the ͓110͔ direction of the
monocrystal; ͑d͒ of the same area at high resolution to show the atomically
flat top surface.
FIG. 2. ͑Color online͒ Refractive index ͑n͒ and Extinction coefficient ͑k͒ of
the films deposited with 48 mTorr Si H8 flow; ͓͑a͒ and ͑b͔͒ reproduce the
3
evolution of ͑n͒ and ͑k͒ with the growth temperature when the films are
deposited on SiO ; ͓͑c͒ and ͑d͔͒ give the comparison of ͑n͒ and ͑k͒ coeffi-
2
cients for a film deposited at 500 °C on ͑001͒Si ͑sample͒ and of reference
samples ͑polycrystalline, amorphous, and monocrystalline Si͒. The compari-
son shows that in this situation, the film presents similar optical parameters
than polycrystalline Si.
the Si H partial pressure to ϳ60 mTorr ͑flow ratio
3
8
F
/FH2 of 0.1%͒. For application reasons the film was
Si H
3
8
2
1
3
doped to 1.10 B/cm using a B H partial pressure of 0.12
2
6
−
1
flow ͑trisilane and silane partial pressures are 48 and 144
mTorr, respectively͒. In the LT range the growth rate is much
larger with trilsilane than with silane ͑almost 20 times larger
at 550 °C͒. The trisilane presents lower decomposition tem-
mTorr.The growth rate is approximately 22 nm min . The
thickness determined from weight measurements was
ϳ150 nm. At this CVD temperature, the film consists of two
parts: a thin c-Si rough layer at the interface ͑about
5
,6
perature than silane ͑Refs. ͒ and thus allows lower thermal
1
5 nm thick͒ and a second thick layer ͑about 140 nm thick͒
budget deposition. From the different surface phases ͑SiO2
fully amorphous ͓Fig. 3͑a͔͒. One can see that the film/
substrate interface is facetted with pronounced ͑111͒ facets
͓Fig. 3͑b͔͒. Such interface morphology has been predicted by
molecular dynamics simulations for crystallization at high
and ͑001͒Si͒, we can see that the total absence of selectivity
during Si H deposition similarly to the deposition with
3
8
SiH4.
8
The deposited layers on ͑001͒Si and on SiO /͑001͒Si
2
temperature. The amorphous microstructure of the thick part
were then investigated by ellipsometry. Refractive index ͑n͒
and extinction coefficient ͑k͒ of the samples were extracted
and compared to the n index and k coefficient of amorphous
of the film is evidenced by cross-section TEM image which
reveals a “salt and pepper” phase contrast at high resolution
typical of amorphous material. Moreover, the selected area
diffraction ͑SAD͒ of the film evidence diffuse rings and the
total absence of diffracted spots on all the areas investigated
confirming the amorphous nature of the layer and the total
͑
a-Si͒, crystalline ͑c-Si͒ films which are, in the same experi-
mental conditions ͑wavelength of 632.8 nm͒, n =4.517
a-Si
͑
n
3.880͒ and ka-Si=0.231 ͑kc-Si=0.019͒, respectively. The
c-Si
optical parameters of the films deposited on SiO have been
absence
of
nanocrystalline
grains
͓Fig.
3͑a͒
2
measured as a function of the substrate temperature ͓Figs.
inset͔.
2͑a͒ and 2͑b͔͒. The curves exhibit a dramatic change of these
Crystallization of these a-Si films on ͑001͒Si is produced
parameters at a temperature of ϳ600 °C. The comparison
with reference samples shows that below 600 °C the Si film
is amorphous, while above 600 °C it is polycrystalline. Con-
cerning the deposition of Si on ͑001͒Si ͑homoepitaxy͒, the
film microstructure is well known to be single crystal. Nev-
ertheless, a deposited monocrystalline layer totally free of
any crystal grain is not able at low temperature. Crystal
grains induce the formation of a polycrystalline layer. Fig-
ures 2͑c͒ and 2͑d͒ give the comparison of the optical param-
eters of the Si film deposited at 500 °C ͑Si H partial pres-
by in situ SPE at 500 °C with a reactor total pressure main-
tained at 60 Torr with H flux. This annealing step consider-
2
ably flattens the c/a interface and suppresses the ͑111͒ facets
well visible at this interface in the sample before SPE. The
c/a interface becomes essentially flat ͑001͒ with an extremely
small portion of ͑111͒ edges. After total crystallization ͑SPE
duration of 600s͒ the film appears single crystal, epitaxially
grown on the substrate and fully free of extended defect ͓Fig.
3͑c͔͒. All the SAD patterns acquired on different areas of the
film only exhibited the ͓110͔ direction ͓Fig. 3͑c͒ inset͔. The
top surface of the film is flat ͓Fig. 3͑d͔͒ and its surface
roughness measured by AFM is below 1 Å, comparable to
the residual roughness of standard bulk Si wafers. In the
same experimental conditions, crystallization of a-Si film
3
8
sure ϳ48 m Torr͒ on ͑001͒ Si with those of reference
samples. It shows that the optical parameters of the film are
very similar to the ones of polycrystalline Si.
In order to obtain an amorphous Si layer on ͑001͒Si, we
decreased again the growth temperature ͑to 400 °C͒ ͑Ref. 7͒
does not occur on insulating areas ͑SiO ͒ and the film re-
2
meanwhile the growth rate was compensated by increasing
mains fully amorphous. This is attributed to the absence of
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1

063102-3
Gouyé et al.
Appl. Phys. Lett. 96, 063102 ͑2010͒
strate ͑and of the a-Si͒ next to these insulating STI areas and
we suggest that this interfacial zone could be suppressed by
increasing the SPE annealing time to complete the crystalli-
zation. The developed SPE process gives then a unique se-
lective crystallization of a-Si on Si substrate and not on SiO2.
Such process can be extended to various structures using
either doped or intrinsic Si.
For the fabrication of a raised S/D MOS structure, a last
step of a-Si removal is needed. This step could be achieved
1
4
by chemical vapor etching using HCl gas at 600 °C.
In conclusion, the two-steps ͑CVD and LT-SPE͒ process
developed during this work provides an original way to fab-
ricate monocrystalline Si free of defects. The characteriza-
tion techniques show that the material is of good quality and
compatible with CMOS technology while requesting a low
thermal budget as compared to conventional processes. Dur-
ing the deposition step fully amorphous Si films were ob-
tained by conventional CVD using Silcore® at 400 °C on
͑001͒Si. The amorphous films were further transformed into
monocrystalline Si, during a second step of solid phase epi-
taxy at 500 °C. We demonstrated, in the last part of this
work, that this two-steps process creates a selective crystal-
FIG. 4. ͑Color online͒ ͑a͒ Schematization of the initial MOS structure; ͑b͒
Schematization of the structure after deposition of a-Si on the initial struc-
ture. The corresponding TEM cross-section images of the experimental a-Si
layer on the different areas are given; ͑c͒ Schematization of the structure
resulting from the selective crystallization process. The corresponding ex-
perimental TEM cross-section images of the a-Si and c-Si on the different
areas are shown.
lization of a-Si on Si͑001͒ and not on SiO areas. Such pro-
2
cess provides an exceptional way to fabricate in a single run
monocrystalline and amorphous films and is highly promis-
ing for the fabrication of raised S/D advanced MOS struc-
tures.
nucleation sites and gives insights on physical properties of
the a/c interface.
In the next part we used the two-steps ͑CVD at 400 °C
and LT-SPE at 500 °C͒ process developed above for the fab-
rication of very shallow raised S/D. Such configuration has
been reported to improve short channel effect ͑SCE͒ and
This work has been carried out in the framework
of IM2NP/STMicroelectronics collaboration. NanoAlliance
DGE and the European Commission through the PullNano
project ͑Contract No. IST-026828͒ are acknowledged for
their financial support.
9
performances of CMOS devices. Raised S/D were usually
formed by selective epitaxial growth ͑SEG͒ in Si–Cl–H
͑
Refs. 9,10 and 11͒ or Si–H systems ͑Refs. 12 and 13͒ that
1
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9
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mation does not occur in SiO . Inversely, on the Si substrate,
2
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remark that in the region close to shallow trench insulation
14
͑
STI͒, the crystallization of a-Si is not perfect. This phenom-
enon is due to the lower temperature ͑Ͻ500 °C͒ of the sub-
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1