Subnanometer-equivalent-oxide-thickness germanium p -metal-oxide- semiconductor field effect transistors fabricated using molecular-beam-deposited high- k /metal gate stack

Article abstract of DOI:10.1063/1.2189456

Metal-oxide-semiconductor field effect transistors (MOSFET) with a thin high- k dielectric were fabricated on bulk n -type germanium substrates. Surface oxides were thermally desorbed in situ by heating the substrates under ultrahigh vacuum conditions. First an ultrathin passivating layer was formed by evaporating germanium in the presence of atomic oxygen and nitrogen supplied from a remote radio frequency plasma source. Subsequently, the HfO2 dielectric was deposited by evaporating hafnium in the presence of atomic oxygen. An in situ TaN metal gate was similarly deposited. Long channel devices were fabricated using a standard process flow. These devices exhibited a low equivalent oxide thickness (EOT) of 0.7 nm with gate leakage less than 15 mA cm2 at VFB +1 V. Device mobility was extracted from Is - Vg and split C-V characteristics. Results indicate a 2× mobility enhancement in Ge p -MOSFET devices compared to Si control devices. The demonstration of subnanometer EOT suggests that high- k gate dielectrics on germanium are scalable to low EOT and suitable for use in ultrascaled MOSFET devices.

Full text of DOI:10.1063/1.2189456

Subnanometer-equivalent-oxide-thickness germanium p -metal-oxide-semiconductor
field effect transistors fabricated using molecular-beam-deposited high- k /metal gate
stack
A. Ritenour, A. Khakifirooz, D. A. Antoniadis, R. Z. Lei, W. Tsai, A. Dimoulas, G. Mavrou, and Y. Panayiotatos
Citation: Applied Physics Letters 88, 132107 (2006); doi: 10.1063/1.2189456
View online: http://dx.doi.org/10.1063/1.2189456
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APPLIED PHYSICS LETTERS 88, 132107 ͑2006͒
Subnanometer-equivalent-oxide-thickness germanium
p-metal-oxide-semiconductor field effect transistors fabricated
using molecular-beam-deposited high-k/metal gate stack
A. Ritenour, A. Khakifirooz, and D. A. Antoniadis
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology,
Cambridge, Massachusetts 02139
R. Z. Leia͒ and W. Tsai
Technology Manufacturing Group, Intel Corporation, Santa Clara, California 95054
A. Dimoulas, G. Mavrou, and Y. Panayiotatos
MBE Laboratory, Institute of Materials Science, National Center for Scientific Research Demokritos,
153 10, Athens, Greece
͑Received 26 October 2005; accepted 27 February 2006; published online 28 March 2006͒
Metal-oxide-semiconductor field effect transistors ͑MOSFET͒ with a thin high-k dielectric were
fabricated on bulk n-type germanium substrates. Surface oxides were thermally desorbed in situ by
heating the substrates under ultrahigh vacuum conditions. First an ultrathin passivating layer was
formed by evaporating germanium in the presence of atomic oxygen and nitrogen supplied from a
remote radio frequency plasma source. Subsequently, the HfO2 dielectric was deposited by
evaporating hafnium in the presence of atomic oxygen. An in situ TaN metal gate was similarly
deposited. Long channel devices were fabricated using a standard process flow. These devices
exhibited a low equivalent oxide thickness ͑EOT͒ of 0.7 nm with gate leakage less than 15 mA/cm2
at VFB+1 V. Device mobility was extracted from Is-Vg and split C-V characteristics. Results
indicate a 2ϫ mobility enhancement in Ge p-MOSFET devices compared to Si control devices. The
demonstration of subnanometer EOT suggests that high-k gate dielectrics on germanium are
scalable to low EOT and suitable for use in ultrascaled MOSFET devices. © 2006 American
Institute of Physics. ͓DOI: 10.1063/1.2189456͔
Improving metal-oxide-semiconductor field effect tran-
sistor ͑MOSFET͒ performance through traditional device
scaling is becoming increasingly difficult. Future improve-
ments in performance will require high mobility semicon-
ductor channels1 such as germanium. One of the main ob-
stacles in realizing Ge transistors is the lack of a good quality
germanium oxide. This can be circumvented by using high-k
gate dielectrics2 that have been extensively investigated over
the last few years for Si-based devices.
Since the demonstration of functional MOSFETs on bulk
Ge channels with ZrO2 ͑Ref. 3͒ and HfO2 ͑Ref. 4͒ gate di-
electrics, there has been significant progress showing perfor-
mance improvement in strained Ge channels.5,6 Several other
papers have demonstrated deep submicron Ge p-MOSFETs
from a 200 mm pilot processing line7 and good quality Ge
MOSFETs on heterogeneous Ge-on-Si ͑Ref. 8͒ and Ge-on-
insulator ͑GOI͒.9 p-MOSFETs show the best performance
while n-MOSFETs show inferior device characteristics for
reasons that are not completely understood at the present
time. Much of the Ge transistor research thus far involves
HfO2 gate dielectrics with thin GeON interfacial layers.
Subnanometer equivalent oxide thickness ͑EOT͒ has been
measured using HfO2/Ge metal-insulator-semiconductor
capacitors10 including those prepared by molecular beam
epitaxy/deposition ͑MBE/MBD͒ techniques.11,12 However,
all functional transistors reported thus far have an EOT larger
than 1 nm raising concerns about the dielectric scalability in
HfO2/Ge MOSFETs. In addition, no results are available on
transistors with MBE/MBD-prepared gate stacks despite the
fact that this method offers alternative surface preparation
techniques12,13 that could improve Ge device performance. In
this work we report Ge p-MOSFETs with MBE/MBD-
prepared TaN/HfO2 gate stacks exhibiting capacitance
equivalent thickness ͑CET͒ of 1.1 nm, which corresponds to
0.7 nm equivalent oxide thickness ͑EOT͒ after quantum me-
chanical correction.
The high-k/metal gate stacks were prepared on n-type
͑100͒ Ge substrates ͑␳ϳ0.025 ⍀ cm͒ by molecular beam
deposition that is described in detail elsewhere.12,13 The na-
tive oxide was thermally desorbed in situ by heating the Ge
substrate to 360 °C for 15 min in ultrahigh vacuum.12,13 An
ultrathin Ge oxynitride layer was then deposited by evapo-
rating Ge at 0.05 Å/s in combined atomic oxygen and nitro-
gen beams generated by a remote radio frequency plasma
source.13 HfO2 was then deposited at 225 °C in an O2 partial
pressure of 4ϫ10−6 Torr by evaporating hafnium at a rate of
0.15 Å/s in the presence of atomic oxygen supplied by the
plasma source. The TaN gate metal was subsequently depos-
ited at room temperature immediately after the oxide depo-
sition without breaking vacuum. Tantalum was evaporated at
a rate of 0.3 Å/s in the presence of atomic nitrogen supplied
by the plasma source. During gate metal deposition, the N2
partial pressure was approximately 1ϫ10−5 Torr. The thick-
nesses of the HfO2 and TaN layers were 5 and 70 nm, re-
spectively, as measured by tunneling electron microscopy.
Control samples with TaN/HfO2 gate stacks on n-type Si
͑␳ϳ0.5 ⍀ cm͒ were also prepared by the same method,
although the native oxide on the Si surface was desorbed
a͒
Electronic mail: rzlei@mtl.mit.edu
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132107-2
Ritenour et al.
Appl. Phys. Lett. 88, 132107 ͑2006͒
FIG. 1. Typical as-measured Is-Vg characteristics for Ge p-MOSFETs. The
current was measured at the source to eliminate drain junction leakage. The
devices exhibited a 0.28 V threshold voltage and 160 mV/decade sub-
threshold swing.
FIG. 3. Typical as-measured split C-V characteristics for Ge p-MOSFETs.
The maximum inversion capacitance corresponds to a CET of 1.1 nm and
EOT of 0.7 nm after quantum mechanical correction.
in situ at much higher temperature ͑810 °C͒. HfO2 was de-
posited directly on the clean Si surface without an interfacial
layer.
Figure 2 shows typical Is-Vd characteristics. Figure 3 shows
the split C-V characteristics of these devices at 100 kHz. The
peak inversion capacitance corresponds to a CET of 1.1 nm
͑without quantum mechanical correction͒. An EOT of 0.7 nm
was extracted by analyzing the inversion side of the split
C-V characteristics using Schred14 which accounts for quan-
tum mechanical effects by self-consistently solving the Pois-
son and Schrödinger equations. Effective mass approxima-
tions were modified within Schred to reflect Ge parameters.
The metal work function and body doping were adjusted to
fit the threshold voltage and the minimum capacitance in the
full split C-V characteristics. With the HfO2 physical thick-
ness fixed at 5 nm, the dielectric constant was modified to fit
the inversion capacitance. The extracted EOT value was con-
firmed by analyzing the accumulation capacitance of MOS
capacitors fabricated in parallel on the same wafer.
Figure 4 shows the typical gate leakage for 10 ␮m gate
length devices and capacitors with an area of 2.5
ϫ10−5 cm2. At VFB+1 V in accumulation, the MOSFET
gate leakage is less than 15 mA/cm2. This low gate leakage
compares favorably to the leakage reported by Tsai et al.15
for 0.75 nm EOT TiN/HfO2/Si p-MOSFET devices ͑less
than 5 A/cm2 at VFB+1 V͒.
MOSFET devices were fabricated using a standard pro-
cess flow. Ring-type structures with gate lengths of 5, 10,
and 20 ␮m were used to eliminate the need for isolation. The
TaN gate electrode was etched using CF4-based reactive ion
etching. The source-drain ͑S/D͒ regions were implanted with
3ϫ1015 cm−2 BF2 at 40 keV. Following S/D implantation,
the HfO2/GeOxNy stack was removed with buffered oxide
etchant ͑BOE͒. Next, S/D activation was performed at
400 °C for 30 min in N2, followed by PECVD oxide depo-
sition, contact photolithography, and contact etching. 30 nm
Ti/450 nm Al metallization was deposited using electron
beam evaporation. Finally a postmetal anneal was performed
at 300 °C for 30 min in forming gas ͑8% H2 in N2͒ at atmo-
spheric pressure.
Typical as-measured characteristics for 10 ␮m gate
length Ge p-MOSFETs are shown in Figs. 1–3. Figure 1
shows the Is-Vg characteristics. The current was measured at
the source to exclude the effect of drain junction leakage to
the substrate. The devices exhibited a 0.28 V threshold volt-
age, 160 mV/decade subthreshold swing, and ON/OFF cur-
rent ratio greater than 103 for a supply voltage of −1.5 V.
The positive threshold voltage and high subthreshold swing
suggest elevated interface trap and oxide charge densities.
FIG. 4. Typical as-measured gate leakage for p-MOSFETs with a gate area
of 6.6ϫ10−5 cm2 and capacitors with an area of 2.5ϫ10−5 cm2. At 1 V, the
gate leakage for both is less than 3 mA/cm2. The EOT for these devices is
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FIG. 2. Typical as-measured Is-Vd characteristics for Ge p-MOSFETs.
0.7 nm.
On: Mon, 24 Nov 2014 13:36:59

132107-3
Ritenour et al.
Appl. Phys. Lett. 88, 132107 ͑2006͒
mobility was enhanced by a factor of 2 compared to
TaN/HfO2/Si control devices.
This work was supported by the MARCO Materials,
Structures, and Devices Center ͑MIT͒ and Intel TMG Exter-
nal Programs.
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the same device. The vertical effective field ͑Eeff͒ was taken
as ͉͑Qb͉ +͉Qinv͉ /3͒/␧Ge, where Qb was calculated from the
body doping. Compared to the silicon control devices, Ge
p-MOSFETs with MBD deposited TaN/HfO2 gate stack
show 2ϫ enhancement in hole mobility. There was no en-
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