Full text of DOI:10.1007/BF02665842

6Jo0ur8nal of ELECTRONIC MATERIALS, Vol. 30, No. 6, 2001
Almeida, Hirsch, Martinka, BoydSp,eacianldIssDueiPnaapner
Improved Morphology and Crystalline Quality of
MBE CdZnTe/Si
L.A.ALMEIDA,1,3 L.HIRSCH,1 M.MARTINKA,1 P.R.BOYD,2 andJ.H.DINAN1
1.—Night Vision & Electronic Sensors Directorate. 2.—Army Research Laboratory. 3.—e-mail:
tony.almeida@nvl.army.mil
We report on continuing efforts to develop a reproducible process for molecular
beam epitaxy of CdZnTe on three-inch, (211) Si wafers. Through a systematic
study of growth parameters, we have significantly improved the crystalline
quality and have reduced the density of typical surface defects. Lower substrate
growth temperatures (~250–280∞C) and higher CdZnTe growth rates improved
the surface morphology of the epilayers by reducing the density of triangular
surface defects. Cyclic thermal annealing was found to reduce the dislocation
density. Epilayers were characterized using Nomarski microscopy, scanning
electron microscopy, x-ray diffraction, defect-decoration etching, and by their
use as substrates for HgCdTe epitaxy.
Key words: CdZnTe, CdTe, heteroepitaxy, Si substrates,
molecular beam epitaxy (MBE)
INTRODUCTION
gen passivated5 ex-situ. Hydrogen was removed in-
situ by heating the wafers to 650∞C. At temperatures
above 450∞C, surfaces were passivated by exposure to
an As4 beam ~ 10–6 mbar. Following As passivation,
the substrate was cooled, and a thin ZnTe layer was
grownbymigrationenhancedepitaxy(MEE).Arange
of ZnTe MEE growth temperatures (230–300∞C) was
investigated. Throughout this temperature range no
significanteffectwasfounduponZnTereflectionhigh
energy electron diffraction (RHEED) patterns nor on
subsequent CdTe epilayer quality, suggesting that
within this temperature range the MEE process is
self-limiting. After deposition of ZnTe, a thin (~150–
Since its inception over a decade ago,1 HgCdTe
heteroepitaxy on Si substrates has matured to a level
where large format (>1000 ¥ 1000 pixels) mid-wave-
length hybrid infrared focal plane arrays have been
demonstrated. An excellent review of the history of
this development is given in Ref. 2. This development
is important not only as an enabler of very large
hybrid arrays but also as a step toward a longer term
goal of a monolithic HgCdTe/Si technology. We have
previously reported3 CdZnTe/Si heteroepitaxy, char-
acterized by mirror-like surface morphologies and
excellent lateral compositional uniformity. However,
these epilayers suffered from a high density (105
– 107 cm–2) of surface defects and relatively poor
crystallinity, as judged from Everson4 defect decora-
tion etching and x-ray diffraction. These defects were
found to be replicated in HgCdTe epilayers deposited
onthesesubstrates.Inthisworkwereportcontinuing
efforts to improve the surface morphology and crys-
talline quality of CdZnTe/Si.
250Å)CdTelayerwasdepositedatalowtemperature
(~200–260∞C),followedbyannealingat~380∞Cunder
Te2 flux. Growth of CdZnTe was carried out at sub-
strate temperatures of ~260–300∞C, and at growth
rates of ~1–5 mm/hour. Typically growth was inter-
rupted periodically (every 1 mm of deposition) and the
epilayer was annealed to ~380∞C under Te flux. Cd1–
yZnyTe epilayers with 0.02 < y < 0.04 were grown by
supplementing the CdTe flux with flux from a cell
containing ZnTe. A majority of the data which follows
were taken for CdTe (y = 0) epilayers. The addition of
ZnTe did not significantly change the surface mor-
phologynortrendsincrystallinequalityexceptwhere
noted below.
EXPERIMENTAL DETAILS
Most relevant details of the experimental set-up
have been reported previously.3 Indium-free, molyb-
denum substrate holders were used to secure three-
inch, nominal (211) Si substrates, which were hydro-
RESULTS
Prior to this study, our CdZnTe epilayers had large
(Received November 21, 2000; accepted January 23, 2001)
608

Improved Morphology and
Crystalline Quality of MBE CdZnTe/Si
609
Fig. 2. Flake-defect density of 25 CdTe/Si epilayers as a function of
growth rate.
Fig. 1. Scanning electron micrograph of defects typical of those
observed at the surface of a CdTe epilayer on a Si substrate.
to cause higher flake-defect densities. Data from
growth set 2 showed elevated densities of flake de-
fects. These higher densities were attributed to a
single event of inadvertent over-heating of the CdTe
source. During growth set 3, special care was taken to
avoid over-heating of the CdTe source material, and
lower growth rates were employed throughout the
growthset.Thesemeasuressuccessfullyreducedflake-
defect densities to ~150/3-inch wafer. The addition of
the relatively small ZnTe fluxes necessary to deposit
Cd1–yZnyTe epilayers with 0.02 < y < 0.04 did not
significantly affect the formation of flake defects.
Crystalline quality was significantly improved by
cyclic thermal annealing during the growth process.
Because of the high temperatures (~380∞C) involved
in this process, Te2 overpressure (~ 2 ¥ 10–6 mbar) was
utilized to maintain smooth surface morphology and
to suppress formation of thermal pit defects. The use
of thermal annealing reduced typical etch pit density
(EPD) values from 1–3 ¥ 107 cm–2 to current values of
2–8¥ 106 cm–2 forepilayersthickerthan12mm.Figure
3 compares EPD values for annealed and unannealed
epilayers as a function of epilayer thickness. Our
lowest observed EPD was 8.0 ¥ 105 cm–2 for a 20 mm
thick CdTe epilayer. Thermal annealing also im-
proved x-ray diffraction full width at half maximum
(FWHM) values, although there was no direct corre-
lation between FWHM and EPD values. Typical
FWHM values were about 100 arcsec for annealed
epilayers. The lowest FWHM value was 71 arcsec for
a 15 mm thick CdTe epilayer. Cd1–yZnyTe epilayers
with 0.02 < y < 0.04 typically exhibited larger FWHM
values (~150 arcsec) and higher EPDs (~2 ¥ 107 cm–2)
than epilayers not containing Zn, when grown under
similar conditions.
densities (~105–107 cm–2) of faceted surface defects.
Figure 1 is a scanning electron micrograph of several
such defects. The density of these defects was dra-
matically reduced by increased CdTe flux and by
decreased growth temperature. Based on this obser-
vation as well as electron microscopy imagery, we
hypothesized that these surface defects were thermal
pitsformedbyexcessiveevaporationfromtheCdZnTe
surface at elevated temperatures. Optimization of
growth rate and/or growth temperature led to typical
defect densities of less than 200 cm–2. It was found
that at growth rates of ~1 mm/hour, a substrate
temperature of less than ~ 290∞C was required to
maintain good surface morphology. To prevent the
formation of these defects during periods of cyclic
annealing, a Te overpressure was used. The addition
of ZnTe flux to deposit Cd1–yZnyTe epilayers with 0.02
< y < 0.04 did not significantly affect the density or
appearance of surface defects.
During the aforementioned investigation, it was
found that excessive CdTe fluxes led to the formation
of “flake” defects. These defects were typically large
(5–50 mm) and irregularly shaped. Their density was
a function of CdTe source temperature and CdTe
source heating schedule history. Higher CdTe source
temperatures ledtohigherdensitiesofflakedefectsand
the occurrence of very large flake-defects (>100 mm).
Excessive heating of the CdTe source for prolonged
periods tended to irreversibly cause flake defect for-
mation in subsequent epilayers even if CdTe flux was
reduced. Figure 2 demonstrates flake-defect forma-
tion as a function of growth rate. Data for Fig. 2 was
taken from 25 CdTe/Si epilayers. One quarter of the
3-inch wafer was cleaved and visually inspected for
flakes. Only flakes visible to the unaided eye were
counted(>2–3mm).Thedatawereclassifiedbygrowth
sets, defined as sets of consecutive growth runs unin-
terruptedbychamberventingandreplenishingofthe
CdTe source material. From Fig. 2 it can be seen that
higher growth rates (i.e., greater CdTe fluxes) tended
The reproducibility of our current process is exhib-
ited by the histogram of Fig. 4, which represents the
FWHM values of 20 consecutively grown CdTe/Si
epilayers. All epilayers were grown under similar
conditions for 15 hours at growth rates ~1 mm/hour.
TheaverageFWHMvalueofallepilayerswas99arcsec
with a standard deviation of 17 arcsec. Nineteen of the

610
Almeida, Hirsch, Martinka, Boyd, and Dinan
Fig. 3. Etch-pit densities for annealed and unannealed CdTe/Si
epilayers.
20 epilayers (95%) had FWHM < 120 arcsec; 50% of
epilayershadFWHM<100arcsecWhilefurtheroptimi-
zation is required to achieve state-of-the-art CdTe/Si
substrates(seeRef.2forexamples),wehavedeveloped
a reproducible process capable of providing substrates
of sufficient quality for subsequent mid-wave infrared
(MWIR) HgCdTe heteroepitaxy.
Fig. 4. Histogram of FWHM values for 20 consecutively grown CdTe/
Si epilayers.
proved the crystalline quality of resulting epilayers,
as measured by defect decoration etching and x-ray
diffraction. Our typical FWHM value for ~15 mm
CdTe epilayer was 100 arcsec, while our best value
was 71 arcsec; EPD values were ~3–8 ¥ 106 cm–2 for
such epilayers. HgCdTe epilayers deposited on these
substratesexhibitedsurfacemorphologieswhichwere
similar to those of the underlying substrates; addi-
tionally, several HgCdTe epilayers exhibited cross-
hatch patterns. The crystalline quality of HgCdTe
was limited by that of the underlying substrate;
FWHM ~100 arcsec and EPD ~9–15 ¥ 106 cm–2.
To demonstrate this, HgCdTe was deposited di-
rectly on CdZnTe/Si wafers. Since the HgCdTe and
CdZnTe/Si growth chambers are connected by an
ultra-highvacuumtransfersystem, nosurfaceprepa-
ration was necessary. Under optimized growth condi-
tions HgCdTe epilayers deposited on CdZnTe/Si sub-
strates exhibited surface morphologies very similar
to those of the CdZnTe/Si substrate. Additionally,
HgCdTeepilayersexhibitedcross-hatchpatternswhen
observed using Nomarski microscopy. The patterns
weresimilartothoseobservedonHgCdTedepositedon
bulk CdZnTe substrates. The appearance of cross-
hatch patterns confirmed the excellent surface mor-
phology of the underlying substrate. EPD values of
HgCdTe epilayers (9–20 ¥ 106 cm–2) were limited by
those of the substrates and typically were observed to
be~2timeshigherthanthoseofunderlyingsubstrates.
FWHM values were typically similar to, or in some
cases slightly lower than, those of the underlying
substrate. Electrical properties of HgCdTe epilayers
deposited on CdZnTe/Si substrates were comparable
to those of HgCdTe deposited on bulk CdZnTe.
ACKNOWLEDGEMENTS
The authors wish to thank Nibir Dhar of the Army
Research Laboratory, Yuanping Chen of EPIR, Ltd.,
and John Cairns of DERA for helpful and insightful
discussions.
REFERENCES
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(1999).
3. N.K.Dhar,P.R.Boyd,M.Martinka,J.H.Dinan,L.A.Almeida,
and N. Goldsman, J. Electron. Mater. 29, 748 (2000).
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Neugebauer, and H.F. Shaake, J. Electron. Mater. 24, 505
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CONCLUSIONS
Through a systematic study of growth parameters,
we have developed a robust process for heteroepitaxy
of CdZnTe on Si substrates. Surface defect densities
were drastically reduced through a combination of
lower growth temperature and increased CdTe flux.
To prevent the formation of surface defects during
cyclicannealingTe2 overpressurewasused.Interrup-
tion of growth with cyclic thermal annealing im-
5. P.J. Taylor, W.A. Jesser, M. Martinka, K.M. Singley, J.H.
Dinan, R.T. Lareau, M.C. Wood, and W.W. Clark III, J. Vac.
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