Structure, chemistry, and electrical performance of silicon oxide-nitride-oxide stacks on silicon

Article abstract of DOI:10.1149/1.1811594

The structure and chemistry of silicon oxide-nitride-oxide (ONO) stacks on silicon with differently processed top oxide layers were analyzed using high-resolution transmission electron microscopy, electron energy loss spectroscopy, secondary ion mass spec

Full text of DOI:10.1149/1.1811594

Journal of The Electrochemical Society, 151 ͑12͒ G833-G838 ͑2004͒
G833
0
013-4651/2004/151͑12͒/G833/6/$7.00 © The Electrochemical Society, Inc.
Structure, Chemistry, and Electrical Performance of Silicon
Oxide-Nitride-Oxide Stacks on Silicon
a,z
Mark Kovler, Yakov Roizin, Menachem Vofsi,b Re ichard D.
b
b
Igor Levin,
c
d e
Leapman, Gary Goodman, Norio Kawada, and Munabu Funahashi
a
National Institute of Standards and Technology, Ceramics Division, Gaithersburg, Maryland 20899, USA
Tower Semiconductor, Limited, Migdal Haemek 23105, Israel
b
c
National Institutes of Health, Division of Bioengineering and Physical Science, Bethesda, Maryland 20892,
USA
d
Charles Evans & Associates, Sunnyvale, California 94086, USA
e
Rigaku Corporation, Akishima-shi, Tokyo 196-8666, Japan
The structure and chemistry of silicon oxide-nitride-oxide ͑ONO͒ stacks on silicon with differently processed top oxide layers
were analyzed using high-resolution transmission electron microscopy, electron energy loss spectroscopy, secondary ion mass
spectroscopy, and X-ray specular reflectometry. The changes observed in the structure and chemistry of the ONO stacks were
correlated with the electrical performance of these stacks in flash-memory devices. The results demonstrated that using larger
thermal budgets to form the top oxide layer yields ͑i͒ broader N distribution across the nitride/oxide interfaces, (ii) reduced H
content at the Si/SiO2 interfaces, (iii) increased density of the top oxide layer, and ultimately, (iv) improved electrical perfor-
mance of ONO-based memory devices.
©
2004 The Electrochemical Society. ͓DOI: 10.1149/1.1811594͔ All rights reserved.
Manuscript submitted December 12, 2003; revised manuscript received April 27, 2004. Available electronically October 29, 2004.
Silicon oxide-nitride-oxide amorphous multilayers ͑ONO stacks͒
attract considerable interest as the charge-storage media in nonvola-
tile memory devices.1 Ultrathin ONO stacks are commonly pre-
a top oxide ͑8-13 nm͒ formed either by nitride reoxidation ͑ONO-S,
ONO-L͒ or deposited using LPCVD from tetraethoxysilane ͑TEOS͒
͑ONO-TEOS͒; the processing conditions are summarized in Table I.
The processing parameters were adjusted to obtain similar thick-
nesses of the corresponding layers in different ONO stacks.
The X-ray specular reflectometry measurements were conducted
,2
pared by thermal growth of a SiO layer ͑bottom oxide͒ on silicon,
2
followed by low-pressure chemical vapor deposition ͑LPCVD͒ of
Si N . Subsequently, the top oxide is either grown by the nitride
3
4
f
2
using automatic grazing incidence Rigaku CXR X-ray reflectome-
ter equipped with a rotating anode generator and a channel-cut Ge
͑220͒ monochromator. Cu K␣1 radiation was used. The incident and
reflected beams were collimated and the reflected intensity was mea-
sured by a scintillation counter. The specular reflectivity was re-
corded in a 2␪ scan from 0 to 10°. The density and thickness of each
layer in the stack, as well as the interfacial roughness, were deter-
mined by analysis of the experimental data using commercial
Rigaku software.
The cross-sectional specimens for TEM were prepared by con-
ventional sectioning, grinding, and polishing followed by dimpling
to a thickness of 25 ␮m. The thinning was completed until perfora-
tion either in the Gatan precision ion-polishing system ͑5 kV, 4°͒ or
in the South Bay ion-milling system ͑5 kV, 10°͒ with the specimen
cooled to Ϫ80°C; both ion-thinning procedures produced similar
results. Phase-contrast imaging and some EELS measurements were
reoxidation or deposited by LPCVD. The typical thickness of indi-
vidual layers in the ONO stacks ranges from 5 to 15 nm. The critical
structural and compositional parameters that affect electrical perfor-
mance of the ONO-based devices include the physical density of the
amorphous oxide/nitride layers and the depth distributions of the
oxygen, nitrogen, and hydrogen atoms. Few systematic studies that
analyze the effect of processing conditions on these parameters in
stacked ONO structures have been reported.3 Some of these studies
-6
observed ONO stacks to consist of well-defined layers of SiO and
2
3,4
Si N
with no significant nitrogen content in the oxide layers.
Other studies revealed considerable concentration of nitrogen in
the top oxide layer of the ONO stacks, as well as the segregation of
3
4
5,6
nitrogen to the bottom SiO /Si interface. Reports of artifacts asso-
2
ciated with nitrogen segregation to the SiO /Si interface during
2
spectroscopic measurements7,8 added to the confusion in the inter-
pretation of the existing data. The optimal ͑from the electrical per-
formance point of view͒ nitrogen profile in the bottom oxide of
conducted in a JEOL-3010 UHR ͑300 kV, LaB source͒ HRTEM
6
9,10
equipped with a GATAN imaging filter ͑GIF͒. Recently, we reported
ONO stacks remains a subject of debate.
At present, incomplete
understanding of the processing-structure/chemistry-properties rela-
tions impedes rational optimization of the processing parameters for
the ONO stacks. The present work is aimed at a systematic study of
these relations in the ONO stacks for flash-memory applications. We
applied both spatially resolved electron energy loss spectroscopy
f
The identification of any commercial product or trade name does not imply en-
dorsement or recommendation by the National Institute of Standards and Technology.
͑
EELS͒ in a transmission electron microscope ͑TEM͒ and secondary
Table I. Processing of ONO structures.
ion mass spectroscopy ͑SIMS͒ to analyze elemental distributions in
the differently processed ONO stacks, while the densities of indi-
vidual layers in these stacks were determined using X-ray specular
reflectometry ͑XRR͒. The results of structural/compositional analy-
ses were subsequently correlated with the electrical performance of
the ONO stacks in flash-memory devices.
Specimen
ONO-S
Processing
1. Bottom oxide: dry oxidation in dilute O at 900°C.
2
2. Silicon nitride: LPCVD in (SiH Cl plus NH )
2
2
3
mixture at 700°C.
. Top oxide: steam oxidation at 1000°C.
3
Experimental
ONO-L
Larger ͑ϫ2͒ initial thickness of nitride layer
Longer nitride reoxidation
The ONO stacks chosen for this study consisted of a thermally
grown bottom oxide ͑6-7 nm͒, a silicon nitride ͑6-15 nm͒ layer
deposited from the mixture of SiCl H and NH using LPCVD, and
ONO-TEOS
ON
TEOS top oxide ͑670°C͒
Stacked oxide-nitride structure
Single-layer thermal oxide
2
2
3
z
E-mail: igor.levin@nist.gov
BOX
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Journal of The Electrochemical Society, 151 ͑12͒ G833-G838 ͑2004͒
Figure 1. Typical HRTEM image of ONO stack. ͑The image was recorded
from the ONO-TEOS specimen.͒
Figure 3. ͑a͒ Profile of the O-K integrated intensity across the ON stack. ͑b͒
Si-L2,3 EELS profiles for the SiO2 and Si N4 layers, and the top surface of
3
the ON stack. The shift of the Si-L2,3 edge at the top surface is consistent
with formation of the oxynitride. These data were recorded using GIF in a
fixed-probe TEM.
that electron-beam irradiation of the nitride layer in the ONO stacks
8
induced nitrogen segregation to the Si/SiO interfaces; the artifact
2
occurred even at relatively low radiation doses. Subsequently, we
developed a procedure for artifact-free EELS measurements of ni-
trogen profiles across the bottom SiO /Si and the top SiO /poly-Si
2
2
8
interfaces. In this procedure, EELS spectrum images were recorded
in a dedicated scanning TEM VG HB501 ͑100 kV, cold field-
emission source͒ equipped with an Enfina EELS system ͑Gatan,
Inc.͒, which incorporates a charge-coupled device ͑CCD͒ detector.
The specimen was cooled down to liquid nitrogen temperature to
prevent contamination buildup. The electron probe ͑1-1.5 nm diam͒
was scanned over an area encompassing the ONO stack, and EELS
spectra containing the Si-L2,3 , O-K, and N-K edges were recorded
at each point ͑pixel͒; the pixel size was kept close to 1 nm. Scans
originating in the Si substrate and poly-Si cap layer were used to
probe the Si/SiO and poly-Si/SiO interfaces, respectively; for each
2
2
scan a freshly irradiated area was used. EELS spectrum images were
acquired using a probe current of ϳ0.1 nA and a dwell time of 0.1 s.
The beam was scanned parallel to the interfaces, and the individual
spectra in the spectrum images acquired were summed along the
scan-line direction to ensure sufficient counting statistics. Specimen
drift during the data collection was corrected automatically by using
a cross-correlation routine. The spectra were further processed to
remove the spectral background, and the intensity under each edge
Figure 2. Profiles of the O-K and N-K integrated intensities across the
ONO-L stack for the beam-scans which originated in the ͑a͒ Si-substrate and
͑b͒ poly-Si cap layer. Similar profiles were obtained for ONO-TEOS.
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Journal of The Electrochemical Society, 151 ͑12͒ G833-G838 ͑2004͒
G835
Figure 4. SIMS depth profiles of elemental distributions in the ͑a͒ BOX and ͑b͒ ON specimens. The contents of N and H were quantified using standards ͑left
axis͒. The data for Si and O were not quantified and are presented in counts/s ͑right axis͒.
was integrated over a 10 eV energy window. Finally, the distribu-
tions of integrated intensities were obtained as a function of spatial
coordinate.
reduced density of negative ͑‘‘chemical’’͒ charge trapped in the top
1
2
oxide layer of this stack. The size of the memory window, defined
as the difference between the values of Vt in the programmed and
the erased states, was 1.5 V. The memory transistors were subjected
to endurance/retention test consisting of 10,000 program/erase
cycles followed by a bake for 1 h at 250°C. The difference in the Vt
values before and after bake ͑closure of the memory window͒ was
used as a measure of the device quality.
SIMS measurements were conducted in a Physical Electronics
ADEPT 1010 quadrupole SIMS instrument. The spectra were ac-
quired using the Cs ϩ 1 keV primary ion beam at 60° to the surface
normal; the primary ion-beam energy and incident angle were cho-
sen to optimize the depth resolution of the analysis. The H and N
concentrations were quantified using silicon oxynitride ͑SiON͒ stan-
dards ͓characterized using nuclear reaction analysis ͑NRA͔͒ and
verified for accuracy with the use of a standardized control sample.
Results and Discussion
Compositional profiles.—EELS.—A typical HRTEM image of
the ONO stack ͑Fig. 1͒ reveals well-defined oxide ͑bright͒ and ni-
tride ͑dark͒ layers. EELS measurements for both ONO-L and ONO-
TEOS specimens yielded similar profiles of O-K and N-K charac-
teristic intensity distributions ͑Fig. 2͒. Artifact-free measurements
revealed no detectable nitrogen segregation to either bottom
SiO /Si ͑Fig. 2a͒ or top SiO /Si ͑Fig. 2b͒ interfaces; the detection
1
8
Detection limits for N and H were estimated to be 4 ϫ 10 and
1
9
3
2
ϫ 10 atoms/cm , respectively. The spatial scale in the SIMS
depth profiles was normalized to the total thickness of the corre-
sponding films, as measured by XRR. Measurements on the ONO
stacks with and without a poly-Si cap layer yielded identical results.
Electrical characterization of ONO-based memory cells was con-
ducted using the microFlash memory transistors ͑Tower Semicon-
ductor, Ltd., Migdal Haemek, Israel͒ and metal-oxide semiconductor
2
2
limit for nitrogen was estimated to be about 1-2 atom %. ͑Note that
the radiation-induced segregation of nitrogen to the same interfaces
was readily detectable.͒ The O-K intensity typically decreased to a
noise level ͑2-3 atom %, 3␴͒ in the middle of the nitride layer ͑Fig.
͑
MOS͒-type capacitors with poly-Si electrodes. The microFlash
2,11
memory devices feature
2 bits per SONOS transistor, where the
local charge trapping occurs in the nitride layer of ONO. The
memory cell is programmed using the channel hot electrons, while
the erasing is accomplished by injecting holes generated by the
band-to-band tunneling. Transistors based on the three types of
ONO stacks ͑ONO-S, ONO-L, and ONO-TEOS, see Table I͒ were
analyzed. Each transistor represented an element of the crosswise-
patterned memory array and featured an effective channel length
L ϭ 0.30 ␮m and channel width ͑word linewidth͒ W ϭ 0.35 ␮m.
The initial ͑before cycling͒ values of a threshold voltage, Vt, ͑drain
current Id ϭ 1 ␮A, and drain bias voltage Vdd ϭ 1.6 V͒ were 1.42
V ͑ONO-S͒, 1.85 V ͑ONO-L͒, and 1.58 V ͑ONO-TEOS͒, respec-
tively. The difference in the initial values of Vt for ONO-S and
ONO-L stacks was associated with the different thickness of the top
oxide. In contrast, lower Vt for ONO-TEOS was attributed to the
2
2
b͒. Occasionally, somewhat larger O-K intensity in the nitride ͑Fig.
a͒ layer was observed and attributed to the beam-induced oxygen/
8
nitrogen diffusion. Existence of such beam-induced diffusion pre-
cluded reliable assessment of oxygen profiles in the nitride layers of
the ONO stacks.
For the ON specimen, the presence of oxygen was detected in the
thin surface layer ͑Fig. 3a͒, which indicates oxidation of the nitride
surface upon exposure to air.
13,14
The energy of the Si-L2,3 edge for
the oxidized nitride surface is higher ͑by about 1 eV͒ than that for
the underlying nitride layer ͑Fig. 3b͒, consistent with formation of a
silicon oxynitride at the surface. This oxidized layer presumably
remained at the interface between the nitride and the top oxide lay-
ers in the final ONO stacks, especially those with a TEOS-deposited
top oxide. Apparent oxidation of the nitride surface correlates with
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G836
Journal of The Electrochemical Society, 151 ͑12͒ G833-G838 ͑2004͒
2
interface, as evidenced by the well-defined plateau in the corre-
Table II. Surface concentrations „atomsÕcm … of N and H. The
sponding nitrogen profile. In contrast, both ONO-S and ONO-L
stacks exhibited a much broader distribution of nitrogen across the
top oxide/nitride interface, which is consistent with the top oxide
grown by nitride reoxidation. Present SIMS data do not provide
conclusive evidence on the exact distribution and the amounts of
nitrogen in the bottom oxide layers of ONO stacks; unfortunately,
back-side SIMS measurements which could resolve these issues
were not available for this study.
H1, H2, and H3 correspond to the top SiO Õpoly-Si interface, the
nitride layer, and the bottom SiO ÕSi interface, respectively.
2
a
2
Sample
N
H1
H2
H3
1
1
1
1
1
3
6
6
6
6
13
13
13
13
13
BOX
ON
5.2 ϫ 10
1.1 ϫ 10
1.0 ϫ 10
1.0 ϫ 10
—
—
—
3.7 ϫ 10
9.0 ϫ 10
3.0 ϫ 10
2.2 ϫ 10
3.7 ϫ 10
15
14
14
14
4.9 ϫ 10
7.0 ϫ 10
7.2 ϫ 10
7.8 ϫ 10
14
14
15
ONO-S
ONO-L
ONO-TEOS 0.8 ϫ 10
2.8 ϫ 10
4.9 ϫ 10
2.4 ϫ 10
XRR measurements.—Both the density and thickness of indi-
vidual layers in the three ONO specimens as measured by XRR
a
The statistical uncertainties ͑2␴͒ are about 20%.
͑Fig. 6͒ are summarized in Table III. The statistical uncertainties
2␴͒ for the thickness and density measurements were about 1%.
͑
The XRR-derived thickness values agreed well with those measured
from the HRTEM images; the scale in the HRTEM images was
calibrated using ͕111͖ lattice fringes of Si. The three ONO speci-
relatively poor reproducibility of electrical properties for the ONO-
TEOS capacitors ͑see the following͒, where the extent of oxidation
could control the electrical performance.
3
mens exhibited similar densities for the bottom oxide ͑2.18 g/cm ͒,
SIMS.—SIMS measurements on the single-layer thermal bottom ox-
ide ͑Fig. 4a͒ revealed a low concentration of nitrogen ͑surface den-
sity 5.2 ϫ 10 atoms/cm , Table II͒ uniformly incorporated in the
which were significantly larger than those of the top oxide layers in
both ONO-S and ONO-TEOS specimens. In contrast, the density of
the top oxide in the ONO-L specimen was comparable to that of the
bottom oxide. The results suggest that longer reoxidation of the
nitride increases the density of the resulting top oxide. The nitride
layers in the three specimens exhibited similar densities of about
1
3
2
layer. The incorporation of N into the oxide layer apparently oc-
curred from the N gas, which was pumped through the chamber
2
15
during the thermal oxidation (T ϭ 900°C). Additionally, the ther-
3
mal oxide contained 3.7 ϫ 1013 atoms/cm2 of hydrogen at the
2.77 g/cm . XRR measurements for the single thermal oxide layer
3
prior to nitride deposition yielded an average density of 2.11 g/cm ,
SiO /Si interface. The hydrogen concentration at the SiO /Si inter-
2
2
3
13
which was significantly lower than the 2.18 g/cm deduced for the
face increased further to 9.0 ϫ 10 upon subsequent deposition
of the nitride layer ͑Fig. 4b, Table III͒; the nitride layer contained
.9 ϫ 10 atoms/cm of hydrogen. The nitrogen content in the ox-
bottom oxide in the ONO stacks. Furthermore, fitting to the experi-
mental XRR data suggested a significant density gradient in the
single thermal oxide layer ͑BOX͒, with the density varying from
1
5
2
4
ide layer of the ON stack was difficult to ascertain because of the
potential trailing of the nitrogen signal into the oxide; still, no clear
3
3
2
.22 g/cm for the bottom third of the layer to 1.99 g/cm for the top
third. These results suggest densification of the upper part of the
bottom oxide layer upon subsequent deposition/growth of the nitride
and the top oxide layers; similar results were reported by Santucci
segregation of the nitrogen to the SiO /Si interface was observed,
2
consistent with the EELS measurements.
The hydrogen profiles for the complete ONO stacks featured
three well-resolved maxima ͑Fig. 5, Table II͒, corresponding to the
1
et al. Such densification can be attributed, at least partly, to the
incorporation of small amounts of nitrogen into the upper part of the
bottom oxide layer. According to XRR, the oxide layers in the ONO
stacks exhibited uniform densities, indicating that the XRR mea-
surements were rather insensitive to the broad nitrogen distributions
in the top oxide layers of the ONO-L and ONO-S specimens.
top SiO /poly-Si interface ͑H1͒, the nitride layer ͑H2͒, and the bot-
2
tom SiO /Si interface ͑H3͒, respectively. The surface density of
2
hydrogen at the SiO /Si interface, H1, decreased progressively on
2
going from ONO-TEOS to ONO-S to ONO-L; that is, the hydrogen
content at the Si/SiO interface diminished with increasing thermal
2
budget used to form the top oxide. The hydrogen content in the
Electrical characterization.—The memory transistors built with
all three ONO stacks ͑ONO-L, ONO-S, and ONO-TEOS͒ featured
overall high endurance/retention characteristics ͑Fig. 7͒. Yet the
transistors based on ONO-L exhibited the lowest reduction of Vt in
the programmed state ͑after cycling and bake͒, while those based on
ONO-TEOS yielded the worst performance. Note that both ONO-L
and ONO-TEOS stacks feature nearly identical thickness for the
nitride layer ͑H2͒ also decreased considerably during growth/
15
2
deposition of the top oxide from 4.9 ϫ 10 atoms/cm for the ON
to (7-7.8) ϫ 1014 atoms/cm for the ONO stacks; however, all three
ONO stacks exhibit similar concentration of hydrogen in the nitride.
This evolution of hydrogen content in the nitride layers is attributed
to the breaking of Si-H bonds at temperatures above 500-600°C
upon growth of the top oxide, while the majority of the N-H bonds,
which are stable up to significantly higher temperatures ͑Ͼ1000°C͒,
remain intact.16
2
g
oxide layers. Furthermore, because the ONO stacks were processed
at the first stages of the device fabrication, the thermal budget used
in the processing of ONO had no influence on either the channel
length or the drain engineering of memory transistors. Therefore, the
differences in the performance of devices based on the different
The SIMS nitrogen depth profiles for the ONO stacks revealed
small ͑Ͻ1 atom/%͒ amounts of nitrogen incorporated into the top
oxide layers; these concentrations were below the detection limits of
the present EELS measurements. ONO-TEOS featured uniform dis-
tribution of nitrogen in the top oxide with a sharp top SiO /Si N
g
In a separate study, we confirmed that different thickness of the nitride layer had no
effect on the Vt degradation.
2
3
4
3
Table III. Thickness „nm… and density „gÕcm … of individual layers in ONO stacks. The statistical uncertainty in the thickness derived from the
HRTEM images is estimated to be Á0.5 nm „2␴…. The relative statistical uncertainties for the thickness and density measured by XRR are 1%
„
2␴….
Bottom oxide
Thickness
Nitride
Thickness
Top oxide
Thickness
Density
XRR
Density
XRR
Density
XRR
Specimen
TEM
XRR
TEM
XRR
TEM
XRR
ONO-S
ONO-L
ONO-TEOS
5.8
6.0
6.0
6.4
6.4
6.0
2.18
2.18
2.22
6.4
7.8
6.3
6.6
8.2
6.1
2.76
2.80
2.77
9.1
12.5
13.1
8.7
12.4
13.4
2.04
2.16
2.04
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Journal of The Electrochemical Society, 151 ͑12͒ G833-G838 ͑2004͒
G837
Figure 5. SIMS depth profiles of elemental distributions in the ͑a͒ ONO-S, ͑b͒ ONO-L, and ͑c͒ ONO-TEOS specimens. The contents of N and H were
quantified using standards ͑left axis͒. The data for Si and O were not quantified and are presented in counts/s ͑right axis͒.
types of ONO are determined primarily by the structure and chem-
istry of individual layers and interfaces in these ONO stacks.
Compared to ONO-TEOS, both ONO-S and ONO-L stacks ex-
hibit significantly broadened top SiO /Si N interface, while
factors is expected to improve the retention characteristics. In par-
ticular, the SiO /Si N interfaces have been suggested to exhibit a
2
3
4
high density of the electron and hole traps due to the presence of
1
3
2
3
4
Si-Si bonds at the interface. Thus, a broader top SiO /Si N in-
2
3
4
ONO-L additionally features lower hydrogen content at the bottom
terfacial region is expected to yield better charge trapping character-
istics. At the same time, lower concentration of hydrogen at the
SiO /Si interface, and higher density of the top oxide. Each of these
2
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G838
Journal of The Electrochemical Society, 151 ͑12͒ G833-G838 ͑2004͒
trode during the erase procedure. At present, we cannot single out
the dominant mechanism leading to the device improvement.
Conclusions
The structure, chemistry, and electrical properties of ONO stacks
with differently processed top oxide layers were compared. Accord-
ing to our results, using larger thermal budgets to fabricate the top
oxide layer yields ͑i͒ lower amount of hydrogen at the bottom
SiO /Si interface, (ii) broader distribution of nitrogen across the
2
top oxide/nitride interface, (iii) higher density of the top oxide
layer, and (iv) superior electrical performance in the resulting
ONO-based memory transistors. Likely, each of the effects (i)-(iii)
contributes to the improved electrical performance of the ONO-L
stacks; however, the relative significance of each factor is difficult to
determine. No nitrogen segregation to the SiO /Si interface was
2
observed by EELS regardless of the thermal budget used to process
the top oxide.
Acknowledgments
Figure 6. Experimental ͑dots͒ and calculated ͑lines͒ X-ray reflectivity pro-
files for ͑a͒ BOX ͑single-layer thermal oxide͒ and ͑b͒ ONO-L.
Fruitful discussions with E. Aloni and V. Gritsenko and technical
support of Y. Feldman and V. Kairys are acknowledged.
Tower Semiconductor Limited assisted in meeting the publication costs of
this article.
bottom SiO /Si interface is known to improve immunity to the hot
carrier degradation. Higher density of the top oxide, as observed in
ONO-L, may suppress parasitic electron injection from a poly elec-
References
2
18
1
. M. H. White, D. A. Adams, and J. Bu, IEEE Circuits Devices Mag., 16͑4͒, 22
2000͒.
͑
2
3
. E. Aloni, S. Kfir, M. Vofsy, and A. Ben-GuiGui, Pat. US 6,583,066 B2 ͑2003͒.
. S. Santucci, L. Lozzi, L. Ottaviano, M. Passacantando, Picozzi, G. Moccia, R.
Alfonsetti, A. Di Giacomo, and P. Fiorani, J. Vac. Sci. Technol. A, 15, 905 ͑1997͒.
. S. Santucci, L. Lozzi, M. Passacantando, A. R. Phani, E. Palumbo, G. Bracchitta,
R. De Tommasis, A. Torsi, R. Alfonsetti, and G. Moccia, J. Non-Cryst. Solids, 245,
4
5
2
24 ͑1999͒.
. T. D. M. Saldago, C. Radtke, C. Krug, J. De Andrade, and I. J. R. Baumvol, J.
Electrochem. Soc., 146, 3788 ͑1999͒.
6. Y. Ma, T. Yasuda, and G. Lucovsky, Appl. Phys. Lett., 64, 2226 ͑1994͒.
7. I. Banerjee and D. Kuzminov, Appl. Phys. Lett., 62, 1541 ͑1993͒.
8. I. Levin, R. D. Leapman, M. Kovler, and Ya. Roizin, Appl. Phys. Lett., 83, 1548
͑
2003͒.
9
. T. Sasaki, K. Kuwazawa, K. Tanaka, J. Kato, and D.-L. Kwong, IEEE Electron
Device Lett., 24, 150 ͑2003͒.
1
0. A. Halliyal, D. K. Foote, H. Komori, and K. W. Au, U.S. Pat. 6,248,628 ͑2001͒.
11. B. Eitan, U.S. Pat. 5,768,192 ͑1998͒.
1
1
1
1
2. Ya. Roizin, M. Gutman, S. Alfassy, and R. Yosefi, in Proceeding of the NonVolatile
Semiconductor Memory Workshop, Monterey, CA, p. 83 ͑2003͒.
3. V. A. Gritsenko, H. Wong, J. B. Xu, R. M. Kwok, I. P. Petrenko, B. A. Zaitsev, Yu.
N. Morokov, and Yu. N. Novikov, J. Appl. Phys., 86, 3234 ͑1999͒.
4. D. Landheer, P. Ma, W. N. Lennard, I. V. Mitchell, and C. McNorgan, J. Vac. Sci.
Technol. A, 18, 2503 ͑2000͒.
5. E. P. Gusev, H. C. Lu, T. Gustafsson, E. Garfunkel, M. L. Green, and D. Brasen, J.
Appl. Phys., 82, 896 ͑1997͒.
1
1
6. F. de Brito Mota, J. F. Justo, and A. Fazzio, J. Appl. Phys., 86, 1843 ͑1999͒.
7. S. Santucci, A. V. la Cecilia, A. DiGiacomo, R. A. Phani, and L. Lozzi, J. Non-
Cryst. Solids, 280, 228 ͑2001͒.
Figure 7. Reduction in the value of Vt for the SONOS 2-bit memory cell
after bake at 250°C for 1 h followed by 10,000 program/erase cycles.
18. T. Hore, H. Iwasaki, and K. Tsuji, IEEE Trans. Electron Devices, 36, 340 ͑1989͒.
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