Compatibility of polycrystalline silicon gate deposition with HfO 2 and Al2O3/HfO2 gate dielectrics

Article abstract of DOI:10.1063/1.1499514

Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO ₂ and Al₂O₃ capped HfO₂ gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO ₂ results in electrical properties much worse compared to similar HfO₂ films using platinum metal gates. However, depositing CVD silicon gates directly onto Al₂O₃ capped HfO₂ showed greater than a 10⁴ times reduction in gate leakage compared to the poly-Si/HfO₂ and poly-Si/SiO₂ controls of similar electrical thickness.

Full text of DOI:10.1063/1.1499514

Compatibility of polycrystalline silicon gate deposition with HfO 2 and Al 2 O 3 / HfO 2
gate dielectrics
D. C. Gilmer, R. Hegde, R. Cotton, R. Garcia, V. Dhandapani, D. Triyoso, D. Roan, A. Franke, R. Rai, L. Prabhu,
C. Hobbs, J. M. Grant, L. La, S. Samavedam, B. Taylor, H. Tseng, and P. Tobin
Citation: Applied Physics Letters 81, 1288 (2002); doi: 10.1063/1.1499514
View online: http://dx.doi.org/10.1063/1.1499514
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/81/7?ver=pdfcov
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APPLIED PHYSICS LETTERS
VOLUME 81, NUMBER 7
12 AUGUST 2002
Compatibility of polycrystalline silicon gate deposition with HfO2
and Al2O3 ÕHfO2 gate dielectrics
D. C. Gilmer,a) R. Hegde, R. Cotton, R. Garcia, V. Dhandapani, D. Triyoso, D. Roan,
A. Franke, R. Rai, L. Prabhu, C. Hobbs, J. M. Grant, L. La, S. Samavedam,
B. Taylor, H. Tseng, and P. Tobin
Digital DNA Laboratories, Advanced Process Development and External Research, Motorola,
3501 Ed Bluestein Boulevard, Austin, Texas 78721
͑Received 2 April 2002; accepted for publication 18 June 2002͒
Polycrystalline-silicon ͑poly-Si͒ gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate
dielectrics are reported. It can be generally stated that chemical vapor deposition ͑CVD͒ silicon
gates using silane deposited directly onto HfO2 results in electrical properties much worse compared
to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly
onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the
poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. © 2002 American Institute
of Physics. ͓DOI: 10.1063/1.1499514͔
Metal–oxide–semiconductor field-effect transistor de-
vices have been aggressively scaled in order to improve per-
formance, but the continuing push to decrease device feature
size is limited by some of the physical properties of the cur-
rent materials. Current technology forecasts show that deep
submicron device scaling will soon require SiO2 gate dielec-
trics be scaled to much less than 2 nm. It is generally ac-
cepted that such scaling will lead to increased tunneling cur-
rents from these very thin SiO2 gate dielectrics resulting in
an unacceptable power consumption and decreased reliabil-
ity. One alternative is to replace SiO2 with a material having
a higher dielectric constant that will allow the use of a
thicker, and therefore less leaky, gate dielectric. Towards this
end, HfO2 has been evaluated to replace SiO2 as a gate di-
electric due to its observed physical stability and calculated
thermodynamic stability against silicon, and because it has a
relatively high dielectric constant (ϳ23)1 and band gap
(ϳ5.8 eV).2 However, we report herein physical and electri-
cal results using metal–oxide–semiconductor capacitors
͑MOSCAPs͒ indicating an incompatibility of HfO2 with a
conventional polycrystalline silicon ͑poly-Si͒ gate process.
Notably, chemical vapor deposition ͑CVD͒ poly-Si gate with
a ZrO2 gate dielectric has already been reported to show
gross incompatibilities.3,4 Although data on devices using
HfO2 gate-dielectric and silicon gates have been reported,
the CVD silicon gates used are often deposited at low tem-
peratures (Ͻϳ580 °C) resulting in amorphous silicon which
can lead to unacceptable dopant depletion effects.3 To cir-
cumvent the observed adverse results with the conventional
poly-Si/HfO2 gate stack, investigations of capping the HfO2
with thin layers of atomic layer deposition ͑ALD͒–Al2O3
before the poly-Si deposition were examined.
on top of some of the HfO2 films using ALD6 with trimethyl-
aluminum ͑TMA͒ precursor. Low pressure chemical vapor
deposition ͑LPCVD͒ silicon gates were deposited using si-
lane (SiH4) at 620 or 540 °C. The 620 °C LPCVD silicon
process is conventionally used for poly-Si gated devices with
SiO2 dielectrics. The 540 °C LPCVD silicon process results
in amorphous silicon films as-deposited which become poly-
crystalline during the subsequent processing anneals. The
silicon gates were implanted with the appropriate dopants,
MOSCAPs were then fabricated using sidewall spacers, Co–
silicide, and forming gas anneal.
Transmission electron microscopy ͑TEM͒ studies of the
interface between the poly-Si gate and HfO2 gate dielectric
indicate no evidence of gross interfacial reaction even after
dopant activation anneals of 1025 °C. However, when de-
positing the poly-Si on top of HfO2 at conventional tempera-
tures of 620 °C, a low density of very large polysilicon
grains is observed. The dark field optical microscope dis-
plays these inhomogeneous grains as a bright spots or ‘‘star-
light’’ ͓Fig. 1͑a͔͒. Cross-sectional TEM ͓Fig. 1͑b͔͒ indicates
an accelerated grain growth of poly-Si and the nucleation of
these features occurs at or very near the HfO2 surface.
The I–V electrical results for 620 °C poly-Si/HfO2
MOSCAPs show very high leakage compared to similar
electrical thickness HfO2 films using platinum metal gates or
similar electrical thickness poly-Si/SiO2 controls. Use of
The HfO2 gate dielectric was deposited on the silicon
substrates by metalorganic chemical vapor deposition
5
͑MOCVD͒ using hafnium-tertiary-butoxide precursor at
550 °C. Thin Al2O3 capping layers were deposited at 300 °C
FIG. 1. ͑a͒ Dark-field optical image (500ϫ) showing observed poly-Si
starlight inhomogeneous grain growth. ͑b͒ Cross-sectional ͑XTEM͒ of a
poly-Si starlight grain.
a͒
Author to whom correspondence should be addressed; electronic mail:
david.gilmer@motorola.com
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0003-6951/2002/81(7)/1288/3/$19.00 1288 © 2002 American Institute of Physics
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Appl. Phys. Lett., Vol. 81, No. 7, 12 August 2002
Gilmer et al.
1289
FIG. 2. XTEM of the poly-Si/Al2O3 capped HfO2 gate stack after a 1000 °C
30 s anneal.
FIG. 4. I–V data for similar electrical thickness films with 620 °C LPCVD
Si-gate and HfO2 , SiO2 , or ALD–Al2O3 capped HfO2 dielectrics.
poly-Si deposited at 540 °C on top of HfO2 resulted in im-
proved electrical properties compared to 620 °C
poly-Si/HfO2 and no inhomogeneous silicon grain growth
was observed. However, leakage for these films was also
very high compared to the platinum metal gate/HfO2 results.
Due to the very high leakage for 620 °C poly-Si/HfO2
stacks, the capacitance–voltage curve is often anomalous
and the maximum capacitance (Cmax) becomes undetermin-
able.
growth is thought to be related to the reported metal induced
lateral crystallization of amorphous silicon films in which
contact of the amorphous film with metals causes very large
grains to grow.7,8 Partial coverage of HfO2 by amorphous
Al2O3 can cover some of these hafnium rich sites ͑i.e., local
HfO2 sites susceptible to reduction during poly-Si deposi-
tion͒ but also adds nucleation sites at the Al2O3 /HfO2 bor-
der. As the amorphous Al2O3 approaches complete coverage
of the HfO2 , the density of available sites for rapid poly-Si
growth decreases until at approximately one monolayer
Al2O3 coverage, none of these sites are available and no
starlight is observed.
Thermodynamic calculations using bulk material data do
not predict a reaction for HfO2 with silicon9 or SiH410 at the
process temperatures and pressures used. However, bulk
thermodynamic values are not generally applicable to atoms
at grain boundaries or surfaces of ultrathin films. The high
leakage current may be related to a partial reduction of HfO2
at grain boundaries and more probably, at grain boundary
triple points where bonding is least perfect. Thus, one plau-
sible reaction could be a reduction of HfO2 at the grain
boundaries during the CVD–Si process by SiH4 , or its de-
composition by-products, which leads to high leakage cur-
rents perhaps by trap assisted tunneling. When the HfO2 is
capped with a thin amorphous Al2O3 layer, the adverse re-
action between HfO2 and SiH4 is prevented resulting in the
low leakage expected for an insulating film.
In summary, it can be generally stated that LPCVD sili-
con gate using SiH4 deposited directly onto HfO2 resulted in
͑1͒ a low density of large poly-Si grains and ͑2͒ much higher
leakage compared to similar HfO2 films using Pt metal gates
and poly-Si/SiO2 controls. However, conventional LPCVD
silicon gates deposited at 620 °C on ALD–Al2O3 capped
HfO2 resulted in the absence of large inhomogeneous
poly-Si grains and well behaved capacitors with greater than
a 104 times reduction in gate leakage compared to films with
the 620 °C poly-Si gate deposited directly on to HfO2 or
620 °C poly-Si/SiO2 controls of similar electrical thickness.
We attribute the two observed adverse phenomena for con-
ventional poly-Si deposited directly on HfO2 to a partial re-
duction of the HfO2 by the poly-Si deposition ambient. In the
first case ͑1͒ the partial reduction occurs locally on the HfO2
surface, while in the second case ͑2͒ the partial reduction
Similar to poly-Si on HfO2 , cross-sectional TEM studies
͑Fig. 2͒ of poly-Si deposited on top of Al2O3 capped HfO2
indicate no evidence of gross interfacial reaction even after
dopant activation anneals of 1000 °C. Figure 3 shows the
relationship of the observed inhomogeneous grain growth, or
starlights ͑see Fig. 1͒, to the number of ALD cycles of Al2O3
applied on top the HfO2 . Ten cycles of ALD–Al2O3 is esti-
mated to be close to one complete monolayer of Al2O3 .
Thus, Fig. 3 indicates that one monolayer of Al2O3 is suffi-
cient to prevent the observed poly-Si inhomogeneous grain
growth seen with the poly-Si/HfO2 gate-stack. Figure 4
shows the I–V electrical results for boron-implanted 620 °C
deposited poly-Si gate/ALD–Al2O3 capped MOCVD–HfO2
MOSCAPs. Upon adjusting for flatband-voltage (Vfb) differ-
ences, an observed leakage reduction greater than a 104
times is measured for ALD–Al2O3 capped HfO2 compared
to films with the 620 °C poly-Si gate deposited directly on to
HfO2 or SiO2 controls of similar electrical thickness.
We speculate that the observed inhomogeneous grain
growth is caused by a low density of locally hafnium rich
sites on the polycrystalline HfO2 surface which promote
poly-Si nucleation and rapid grain growth. These hafnium
rich sites are attributed to local reduction of the HfO2 surface
in the poly-Si deposition ambient. The inhomogeneous grain
FIG. 3. Density of observed starlight inhomogeneous grains vs the number
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of ALD–Al2O3 cycles (1 cycleϭTMA pulseϩH2O pulse).
occurs at grain boundary triple points.
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1290
Appl. Phys. Lett., Vol. 81, No. 7, 12 August 2002
Gilmer et al.
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