Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO2/Si metal-oxide-semiconductor structures

Article abstract of DOI:10.1063/1.1468273

We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO₂/p-Si metal-oxide-semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer- deposition (ALD)-TiN as manifested by an excellent interface trap density (D_it) as low as ～4×10¹⁰eV^-1cm ^-2 near the Si midgap. ALD-TiN improved the D_it level of MOS systems on both thin SiO₂ and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD-TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD-TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.

Full text of DOI:10.1063/1.1468273

Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO 2 / Si
metal–oxide–semiconductor structures
Dae-Gyu Park, Kwan-Yong Lim, Heung-Jae Cho, Tae-Ho Cha, In-Seok Yeo, Jae-Sung Roh, and Jin Won Park
Citation: Applied Physics Letters 80, 2514 (2002); doi: 10.1063/1.1468273
View online: http://dx.doi.org/10.1063/1.1468273
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APPLIED PHYSICS LETTERS
VOLUME 80, NUMBER 14
8 APRIL 2002
Impact of atomic-layer-deposited TiN on the gate oxide quality
of WÕTiNÕSiO ÕSi metal–oxide–semiconductor structures
2
a)
Dae-Gyu Park, Kwan-Yong Lim, Heung-Jae Cho, Tae-Ho Cha, In-Seok Yeo,
Jae-Sung Roh, and Jin Won Park
Memory Research and Development Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si,
Kyoungki-do 467-701, Korea
͑
Received 24 September 2001; accepted for publication 9 February 2002͒
We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of
W/TiN/SiO /p-Si metal–oxide–semiconductor ͑MOS͒ systems. Damage-free gate oxide quality
2
was attained with atomic-layer-deposition ͑ALD͒–TiN as manifested by an excellent interface trap
1
0
Ϫ1
Ϫ2
density (D ) as low as ϳ4ϫ10 eV cm near the Si midgap. ALD–TiN improved the D level
it
it
of MOS systems on both thin SiO and high-permittivity ͑high-k͒ gate dielectrics. The leakage
2
current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with
sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness ͑CET͒. Less
chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against
postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate
process. © 2002 American Institute of Physics. ͓DOI: 10.1063/1.1468273͔
Direct metal gate has been studied to overcome the ob-
stacles of polycrystalline-Si ͑poly-Si͒ gate structures such as
gate depletion, boron penetration, and high resistance in nar-
grown by rapid thermal oxidation at 750 °C and ZrO films
2
were prepared by ALD using ZrCl and H O at 350 °C fol-
4
2
lowed by dielectric improvement anneal at 600 °C in O . As
2
1
–16
row gate line.
Because of good thermal stability and mid-
a direct metal gate, TiN films ͑30 nm͒ were prepared by
gap work function, refractory metals such as W and TiN have
PVD, CVD, and ALD methods. PVD–TiN films were reac-
tive sputtered under the power density of 1–7 W/cm at
300 °C and CVD–TiN films prepared at 650 °C using TiCl4
2
attracted lots of attention for sub-100 nm metal–oxide–
semiconductor ͑MOS͒ device applications.2
–4,8–13
Unfortu-
and NH . For ALD–TiN deposition, we used a traveling
nately, direct metal gate prepared by physical vapor deposi-
tion ͑PVD͒ method can create defects such as metal
penetration and plasma damages which lead to reliability
problems of gate dielectrics.5 To circumvent these ob-
stacles, chemical vapor deposition ͑CVD͒–TiN process was
3
wave reactor by the cyclic dosing of TiCl and NH sources
4
3
at the substrate temperature (T ) of 450 °C. PVD–W ͑70
s
–8
nm͒ was then deposited at 200 °C, followed by the patterning
of square shape electrodes with various active areas of 4
Ϫ6
Ϫ4
2
recently employed.8
–12
ϫ10 –4ϫ10 cm . Postmetal anneal ͑PMA͒ was carried
out by furnace anneal at 450 °C in forming gas ͑10%
H /90%N ͒ or at 800 °C in N for 30 min or by rapid ther-
However, CVD–TiN prepared by
metalorganic precursors introduced high carbon impurity and
reliability problems,10 while the film by TiCl and NH gen-
2
2
2
4
3
mal anneal ͑RTA͒ at 950 °C in N for 20 s.
2
erated unstable capacitance equivalent thickness ͑CET͒
Electrical characterization of the W/TiN/SiO /Si MOS
2
variation and reliability degradation due to high chlorine
8
,12
capacitor was performed in a light-free probe station. To
scrutinize the level of interface traps with deposition method
and PMA, capacitance–voltage (C–V) and conductance
͑
͓Cl͔͒ content.
hurdles, we approached a process, atomic-layer deposition
ALD͒, for TiN. The ALD approach may minimize impurity
In order to prevent aforementioned
͑
measurements were carried out using a HP4284A LCR
incorporation as well as remove the metal and/or plasma
damages. In this letter, we present a damage-free direct metal
gate using ALD–TiN process as confirmed by an excellent
meter.8
,17,18
The gate current density–voltage (J–V) and
time-dependent dielectric breakdown measurements of the
W/TiN/SiO /p-Si MOS capacitors were performed using a
2
interface trap density (D ) with reduced gate leakage cur-
it
HP4156B. The chlorine content in the TiN/SiO was probed
2
rent. Further, improved reliability characteristics in combina-
tion with stable CET variation are demonstrated.
ϩ
by a PHI-6300 secondary ion mass spectrometer using a Cs
primary ion source of ϳ3 keV beam energy.
Shown in Table I are typical characteristics of various
TiN ͑30 nm͒ films we used. PVD–TiN showed relatively low
MOS capacitors composed of W/TiN/SiO /p-Si were
2
fabricated using 8 in., p-type Si ͑100͒ wafers with a resistiv-
ity of 8–10 ⍀ cm. After formation of field oxide, a standard
pregate cleaning was employed and followed by the growth
of controlled oxide ͑3 nm͒ in wet ambient at 750 °C. In ad-
TABLE I. Typical characteristics of TiN ͑30 nm͒ films prepared by various
deposition methods.
dition,
the
MOS
capacitors
comprised
of
ZrO (5 nm)/SiO (ϳ0.7 nm)/p-Si structure were also fabri-
cated to investigate the effect of TiN deposition method on
TiN
͑30 nm͒
Ts
͑°C͒
Crystal
orientation
Resistivity
͑␮⍀ cm͒
͓Cl͔
2
2
(1ϫ1018 atoms/cm3)
the high-k gate dielectrics. The ultrathin interfacial SiO was
2
PVD–TiN
CVD–TiN
ALD–TiN
300
650
450
͑111͒
͑200͒
͑111͒/͑200͒
110–120
ϳ150
ϳ80
ϳ2
ϳ250
ϳ52
a͒Electronic mail: memspark@ieee.org
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003-6951/2002/80(14)/2514/3/$19.00 2514 © 2002 American Institute of Physics
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0
1

Appl. Phys. Lett., Vol. 80, No. 14, 8 April 2002
Park et al.
2515
FIG. 3. Interface trap density (D ) of W/TiN/SiO /p-Si MOS capacitors as
it
2
a function of PMA.
FIG. 1. High-frequency C–V and G/␻–V characteristics of W/TiN/SiO2
(
ϳ3 nm)/p-Si MOS structures after FGA at 450 °C for 30 min. The inset
displays G/␻–V curves of CVD– and ALD–TiN films. The square elec-
of ϳ5.4ϫ10 eVϪ1 cmϪ2 near the Si midgap after FGA and
10
Ϫ4
Ϫ2
trode area is 4ϫ10 cm
.
ϳ4ϫ1010 eVϪ1 cm after furnace anneal over 800 °C and
FGA were obtained. The present Dit value attained with
ALD–TiN is comparable to the level of poly-Si gate, indi-
cating that damage-free direct metal gate process can be re-
Ϫ2
resistivity and negligible chlorine content. In particular,
CVD–TiN displayed relatively high ͓Cl͔ (ϳ2.5
2
0
3
ϫ10 atoms/cm ) and a resistivity ͑␳͒ of ϳ150 ␮⍀ cm,
whereas ALD–TiN exhibited the ͓Cl͔ as small as ϳ5.2
alized using ALD approach. Second, the D of PVD–TiN
it
11
Ϫ1
Ϫ2
decreases from ϳ2.7ϫ10 eV cm
ϳ7.8ϫ10 eV cm
͑FGA only͒ to
͑furnace anneal at 800 °C and
1
9
3
ϫ10 atoms/cm and a resistivity of ϳ80 ␮⍀ cm. The
lower ␳ of ALD–TiN than that of CVD–TiN is attributed to
the lower ͓Cl͔, consistent with earlier results.19 We also note
that the lower ␳ of ALD–TiN over PVD–TiN is related with
larger grain size as observed by transmission electron mi-
croscopy ͑not shown͒.
10
Ϫ1
Ϫ2
FGA͒, suggesting that the high temperature anneal in com-
bination with FGA is essential to anneal out the damages
introduced during the PVD process. On the other hand, the
10
Ϫ1
Ϫ2
Dit with CVD–TiN was ϳ8ϫ10 eV cm
after FGA
11
Ϫ2
and this has slightly increased to ϳ1.2ϫ10 eV cm after
PMA at Ͼ800 °C and FGA ͑Fig. 3͒, which is under investi-
Figure 1 shows high-frequency C–V and conductance
loss
(G/␻)–V
characteristics
of
various
gation. The lower D values with ALD– and CVD–TiN after
it
TiN/SiO (3 nm)/p-Si MOS capacitors after forming gas an-
2
FGA are ascribed to both the damage-free deposition and Cl
neal ͑FGA͒ at 450 °C. The conductance loss peaks shown in
8,20
passivation at the dangling bonds of SiO /Si interfaces.
2
the inset describe the evolutionary changes of D with depo-
it
Figure
4
exhibits
CET
variation
of
the
1
7,18
sition method.
The loss values of ϳ7 pF for PVD–TiN,
W/TiN/SiO (3 nm)/p-Si MOS capacitors with deposition
2
1
.95 pF for CVD–TiN, and 1.29 pF for ALD–TiN corre-
scheme and PMA. The CET increases in the order of PVD–
TiN, ALD–TiN, and CVD–TiN. The lowest CET ͑ϳ3.08
nm͒ was attained with PVD–TiN after FGA, while a slight
CET increase ͑ϳ0.12 nm͒ was observed after RTA at 950 °C
and FGA. The CET of MOS capacitor gated with ALD–TiN
was ϳ3.45 nm and negligible CET change ͑ϳ0.03 nm͒ was
1
1
10
spond to the D values of ϳ4ϫ10 , ϳ8ϫ10 , and ϳ5.9
ϫ10 eV cm , respectively.
it
Ϫ2
1
0
Ϫ1
For more accurate D extraction, the G/␻Ϫlog ␻ char-
it
acteristics of the W/TiN/SiO (3 nm)/p-Si MOS capacitors
2
after FGA were explored for a given surface potential ͑Fig.
2
͒, and extracted D values with various PMA are summa-
it
rized in Fig. 3. There are several important features. First, the
D of ALD–TiN gate structure was the lowest. The D level
it
it
FIG. 2. The measured conductance loss (G/␻)-log ␻ plots of various
TiN/SiO (ϳ3 nm)/p-Si MOS capacitor as a function of gate voltage and
2
PMA. The PMA was carried out by FGA at 450 °C. The applied gate volt-
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ages or surface potentials are also shown.
FIG. 4. CET variation of W/TiN/SiO /p-Si MOS capacitors with PMA.
2
1
32.174.255.116 On: Sun, 30 Nov 2014 22:03:27

2516
Appl. Phys. Lett., Vol. 80, No. 14, 8 April 2002
Park et al.
using ALD–TiN is about 2–3 orders of magnitude lower
than that using PVD–TiN. In particular, the low-field leak-
age current level in the ALD–TiN gate case is distinctly
lower than that with poly-Si at the similar CET, possibly due
to the physically thicker SiO . A projected 10 year lifetime
2
as measured by the constant voltage stress is shown in Fig.
6
͑b͒. MOS capacitors gated with ALD–TiN exhibited the
highest critical electric field (Eox,critical) over PVD– and
CVD–TiN, demonstrating reliable gate oxide integrity. The
lowest Eox,critical for CVD–TiN electrode case is attributed to
the high residual Cl in TiN which can diffuse to the gate
oxide, resulting in the formation of Cl-related trap site.12
In summary, we explored an unique damage-free direct
metal gate process using ALD–TiN with low D , negligible
it
FIG. 5. C–V characteristics of TiN/ZrO (5 nm)/SiO (0.7 nm)/p-Si MOS
2
2
CET variation, reduced gate leakage current, and robust re-
liability characteristics. The lower level of Cl content by
ALD process was pivotal in achieving negligible CET varia-
tion against PMA and better gate oxide reliability. Selection
of pertinent precursors for impurity control would be critical
for future metal gate technology using ALD.
capacitors as a function of TiN deposition method at 100 kHz. The conduc-
tance loss (G/␻)–V characteristics are displayed in the inset. Those capaci-
tors were experienced a PMA of furnace anneal at 600 °C and FGA.
achieved against high thermal budget at 950 °C; however,
noticeable CET increase of ϳ0.35 nm was observed with
CVD–TiN. We also observed that ALD–TiN films deposited
The authors would like to thank J.-Y. Kim, Y.-S. Kim,
J.-M. Yang, J.-J. Kim, J.-K. Ko, and S.-Y. Lee for materials
preparation and analyses. They also thank H.-J. Lee and
B.-Y. Choi of PKL, S.-K. Lee of IPS, and Henk de Waard of
ASM America for the deposition of ALD–TiN and ZrO2
films.
at low T ͑Ͻ350 °C͒ showed higher ͓Cl͔ incorporation, so
s
2
1
higher resistivity films and CET increase with PMA.
The effects of TiN deposition method on the high-k gate
dielectrics are depicted in Fig. 5, displaying C–V curves of
the TiN/ZrO (5 nm)/SiO (ϳ0.7 nm)/p-Si MOS capacitors.
2
2
The G/␻–V characteristics are shown in the inset. The CET
value with ALD–TiN is slightly higher than that with PVD–
1
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FIG. 6. ͑a͒ J–V curves and ͑b͒
a
10 year lifetime of
W/TiN/SiO (3 nm)/p-Si MOS structures with PMA ͑furnace anneal at
2
ϩ
18
8
00 °C and FGA͒ measured at room temperature. The
n
poly-
Si/SiO /p-Si MOS structure having the similar CET was also compared in
2
1
2
2
9
0
1
Fig. 6͑a͒. Each data point in Fig. 6͑b͒ represents mean time to failure of 40
data points on the 8 in. wafers. The Eox,critical of over-9.2 MV/cm ͑Ϫ3.38 V
at CETϭ3.5 mm͒ may be used with ALD–TiN at room temperature, while
the Eox,critical of Ϫ8.6 MV/cm ͑Ϫ3.02 V at CETϭ3.32 nm͒ and Ϫ8.2
MV/cm ͑Ϫ3.14 V at CETϭ3.8 nm͒ can be used for PVD– and CVD–TiN,
respectively.
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