Growing high-performance tunneling oxide by CF4 plasma treatment

Article abstract of DOI:10.1149/1.1527052

Thin tunneling oxides grown on a CF₄ pretreated silicon substrate were prepared and investigated for the first time. The tunneling current of the CF₄-treated oxide is about three orders of magnitude higher than that of thermal oxide;

Full text of DOI:10.1149/1.1527052

Journal of The Electrochemical Society, 150 ͑1͒ G33-G38 ͑2003͒
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0013-4651/2003/150͑1͒/G33/6/$7.00 © The Electrochemical Society, Inc.
Growing High-Performance Tunneling Oxide by CF4
Plasma Pretreatment
Tzu Yun Chang, Jam Wem Lee, Tan Fu Lei,z Chung-Len Lee,
and Huang Chun Wen
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Thin tunneling oxides grown on a CF4 pretreated silicon substrate were prepared and investigated for the first time. The tunneling
current of the CF4-treated oxide is about three orders of magnitude higher than that of thermal oxide; furthermore, the stress-
induced anomalous current and low electric field leakage current were greatly suppressed. The improvement was attributed to the
incorporation of fluorine in the oxide region. Both control and CF4-treated devices exhibited comparable channel mobility.
However, pretreatment with CF4 markedly improved the reliability of the insulator. This oxide is highly promising for fabricating
low-voltage electrically erasable and programmable read-only memories ͑EEPROMs͒ without increasing the complexity of the
process.
© 2002 The Electrochemical Society. ͓DOI: 10.1149/1.1527052͔ All rights reserved.
Manuscript submitted March 28, 2002; revised manuscript received July 11, 2002 Available electronically December 3, 2002.
Electrically erasable and programmable read-only memories
͑EEPROMs͒ with low operating voltages are necessary to lower the
power consumption of portable electric products. A feasible method
of reducing the power consumption is to reduce the thickness of the
gate oxide. Equivalent electric fields and tunneling currents can be
maintained when devices operate at low voltage. However, the
thickness of the oxide is limited to around 6.0 nm due to the stress-
induced-leakage-current, or SILC effect.1,2 Reducing the barrier
height of silicon dioxide is another approach to lowering the oper-
ating voltage. The operating voltage can be done by increasing the
silicon surface roughness,3 changing the doping concentration of
polysilicon gates,4,5 implanting fluorine into silicon before gate oxi-
dation, and gate oxidation in NO or similar gases.6 Thin fluorinated
oxides have been investigated and found to have lower barrier
height than silicon dioxide.7 Fluorinated oxides have also been
widely studied for their high resistance against ionized radiation and
hot electrons.2,8-10 Additionally, the nitrided oxide grown on
F-implanted silicon was found to be able to suppress anomalous
leakage currents.11 Consequently, metal-oxide semiconductor field
effect transistors ͑MOSFETs͒ fabricated with fluorinated oxides ex-
hibit a decreased interface trap density. Moreover, fluorinated oxide
interfaces are more resistant to hot carrier damage than thermal ox-
ides. Several methods were proposed for fabricating oxide;8-11 how-
ever, few methods are compatible with modern integrated circuit
͑IC͒ processes.
Plasma-containing fluorine has been extensively used in
ultralarge-scale integrated ͑ULSI͒ technology. Fluorinated oxides
exhibit high resistance against ionized radiation and hot carriers.10,12
Recently, the authors reported a simple fabrication process to grow
fluorinated oxides with a high tunneling current and low leakage
current.13 This study investigates the electrical and physical charac-
teristics of MOSFETs with this fluorinated oxide, pretreated with
CF4 plasma.
Experimental
Metal oxide semiconductor ͑MOS͒ capacitors and n-channel
MOSFETs with fabricated oxides were constructed. First, p-type
͑100͒ wafers with sheet resistance of 15-20 ⍀-cm underwent RCA
cleaning and were then treated with CF4 plasma in a plasma-
enhanced chemical vapor deposition ͑PECVD͒ chamber at 300°C
and a pressure of 600 mTorr. The plasma treatment times were 1, 2,
3, and 5 min. The radio frequency ͑rf͒ power was set to 10 W. In
contrast, the control sample was cleaned without CF4 plasma treat-
ment. Following the standard RCA cleaning, a thin oxide, with a
thickness of 5.0 nm, was then grown on those wafers at 900°C in
Figure 1. ͑a͒ Positive and ͑b͒ negative J-E characteristics of the five
samples: samples were CF4 plasma treated for 1, 2, 3, and 5 min, respec-
tively.
z E-mail: tflei@cc.nctu.edu.tw

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Figure 3. High-frequency C-V characteristics of the five samples: samples
were CF4 plasma treated for 1, 2, 3, and 5 min, respectively.
Figure 2. ͑a͒ XPS profiles of the control sample and CF4-plasma-treated
wafer. The treatment was at a power of 10 W for 5 min. ͑b͒ SIMS analysis of
the silicon substrate treated by CF4 plasma at 10 W for 5 min.
diluted O2 ambient and annealed in N2O at 900°C for 5 min. A 300
nm polysilicon film was then deposited. After the gate electrode was
defined, gate, source, and drain were doped by phosphorous ion
implantation. The substrate contact was doped by boron ion implan-
tation. A rapid thermal anneal ͑RTA͒ process, lasting 30 s performed
at 1000°C, was used for activation. Finally, contact holes were
etched by reactive ion etching ͑RIE͒ and Al pads were also defined.
The electrical thickness of the oxide was determined by
capacitance-voltage ͑C-V͒ measurement, and the physical thickness
was characterized by using transmission electron microscopy
͑TEM͒. The current-voltage ͑I-V͒, leakage current, and reliability
characteristics were measured using an HP 4156B. Fluorine incor-
poration was determined by secondary ion mass spectroscopy
͑SIMS͒ and X-ray photoelectron spectroscopy ͑XPS͒ analysis.
Figure 4. ͑a͒ Characteristics of anomalous leakage current of the control
sample and the 5 min samples, and ͑b͒ the integral of the area from Vg ϭ
Ϫ 0.5 to 0.5 V: ͚(⌬VIg) under the curve of the anomalous current of the
five samples. Samples 0.1, 1.0, and 10.0 C were stressed at 0.1, 1.0, and 10.0
C/cm2, respectively.

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Figure 6. Weibull distribution plots of the Qbd of the control and 5 min
samples.
bonds in the oxides.11,12,15 In the high-electric-field region, the
higher tunneling current is also the result of a lower barrier height of
the SiOF layer.
Both the control and the samples that were CF4 plasma-treated
for 5 min were analyzed by XPS, as shown in Fig. 2a, to elucidate
the effect of the CF4 plasma treatment. Strong signals associated
with fluorine bonds were detected. However, no fluorine signals
were observed in the control sample. Therefore, fluorine is indeed
incorporated into the silicon substrate during CF4 plasma treatment.
The location of the fluorine incorporated during plasma treatment
was discerned by SIMS. Figure 2b shows the SIMS depth profile of
the silicon substrate treated by CF4 plasma. The SIMS profile shows
that fluorine atoms are located in a thin layer ͑about 3.0 nm͒ on the
surface of the silicon wafer. That is, fluorine is confined in the
SiO2 /Si interface region during oxidation. The SIMS analyses show
that much density of fluorine was incorporated only at the interface,
instead of in the substrate. This method is superior to the fluorine-
implant method, which causes a high concentration of fluorine to be
found in the channel region.
Figure 3 plots the high-frequency C-V curves of these five
samples pretreated under different CF4 treatment conditions. The
symbols that represented different CF4 plasma conditions are the
same as those used previously. The samples pretreated with CF4
plasma exhibited an increase in electrical thickness ͑that is, they
have a lower capacitance͒. The 5 min sample had a 10% greater
thickness than the control. Although fluorine has been reported to
enhance the rate of oxidation by replacing Si-O bonds with Si-F
bonds,15,16 this did not occur in the samples considered here. In fact,
the physical thickness of both the control and the treated samples
observed by transmission electron microscope ͑TEM͒ are almost the
same, as shown in the insert in Fig. 3. For a particular physical
thickness, increase in the electrical thickness should reduce the di-
electric constant, due to fluorine incorporation, as for the low-k ma-
terial SiOF.
Figure 5. ͑a͒ SILC characteristics of the control and 5 min samples and ͑b͒
the integral of the area of the ⌬Ig from Vg ϭ 1-3 V; that is: ͚(⌬V(Ig-Igo),
where the Ig is the measured oxide leakage current and Igo is the leakage
current of the fresh samples.
Results and Discussion
Figure 1 shows the J-E characteristics of the samples with dif-
ferent process times under ͑a͒ positive and ͑b͒ negative gate volt-
ages. The symbols indicate samples treated with CF4 plasma treat-
ment for 1, 2, 3, and 5 min. The tunneling current of the oxide
increases with the treatment time. The tunneling current was espe-
cially high for the 5 min sample with the negative gate bias. The
tunneling current of the 5 min sample was found to be about three
orders of magnitude higher than that of the control sample, due to
the lower barrier height of the gate oxide after CF4 pretreatment.14
Under positive gate bias, the leakage current in the low-electric-field
(4-6 MV/cm) region decreases as the plasma treatment time in-
creases. The improvement was attributed to the fluorine incorpora-
tion at the SiO2 /Si interface, resulting in Si-F bond formation. Thus,
the leakage current in the low-electric-field regime was suppressed
because the Si-F bonds could passivate the defects and the dangling
Figure 4a presents the characteristics of anomalous leakage cur-
rent of the control sample and the 5 min pretreated sample. An
additional CF4 process was found to suppress the anomalous leak-
age current. Figure 4b shows the integral of the area from Vg
ϭ
Ϫ 0.5 to 0.5 V: ⌺ (⌬VIg) under the curve of the anomalous
currents for the five samples. Samples were stressed at 0.1, 1.0, and
10.0 C/cm2, respectively. The leakage current of 5 min CF4 plasma-
treated sample was lower than that of the control. After constant
current stress, the leakage current of the control sample increased

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Figure 8. ͑a͒ Drain current vs. gate voltage curves and transconductance vs.
gate voltage curves and ͑b͒ drain current vs. drain voltage curves of the
control and the 5 min samples.
induced leakage current at a low electric field ͑3-6 MV/cm͒ than the
control. Additionally, Fig. 5b shows the integral of the area under
the curve of ⌬I from V ϭ 1-3 V, ⌺ ⌬V(I Ϫ I ) , where I is
͓
͔
g
g
g
go
g
the measured oxide leakage current and Igo is the leakage current of
the fresh samples. Clearly, oxides grown by CF4 pretreatment are
more resistant to constant current stress. This method can greatly
improve the reliability of the EEPROMs. The improvement can be
further enhanced with more fluorine incorporation. In fact, when
measuring wafers at a constant current stress, a higher tunneling
current of the oxide is another important factor affecting reliability.
Figure 6 shows the Weibull distribution plots of charge-to-
breakdown (Qbd) for the control and 5 min samples. Qbd is a useful
index of the quality of the oxides in EEPROM applications, since a
high-density current tunnels through the oxides during programming
and erasing. In this figure, the 5 min sample exhibits a higher Qbd
than the control. Stronger Si-F bonds are suggested perhaps to be
able to effectively replace Si-H or Si-OH bonds and enhance the
charge-to-breakdown performance. Consequently, the oxides grown
on a CF4-pretreated wafer are very promising as tunneling oxides in
EEPROMs.
Figure 7. AFM images of the silicon substrate surface of the ͑a͒ nontreated
sample, ͑b͒ sample treated with CF4 for 3 min, and ͑c͒ sample treated with
CF4 for 5 min.
rapidly. However, the leakage current of the 5 min sample decreased
in the first stage of stress and then increased slowly, not only in the
case of the 5 min sample but also for all the pretreated samples.
Briefly, the anomalous leakage current decreased as the CF4 plasma
treatment time increased. Incorporating fluorine into the oxide re-
gion significantly suppressed the anomalous current.
Figure 5a plots SILC characteristics for the control and 5 min
samples. The 5 min sample has a higher resistance against stress-
CF4 plasma is commonly used for Si-etching applications. A
rough surface degrades device performance. Atomic force micros-

Journal of The Electrochemical Society, 150 ͑1͒ G33-G38 ͑2003͒
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Figure 10. Delta transconductance vs. injected charge fluence curves of the
control and 5 min samples.
drain voltage curves of the control sample and the 5 min sample,
shown in Fig. 8b, both exhibit the reduction of channel mobility, as
mentioned previously.
Figure 9 exhibits the degradation of transconductance under dif-
ferent stress charges for ͑a͒ the control sample and ͑b͒ the 5 min
sample. Hot-carrier stress conditions are measured by applying ϩ10
mA from the gate, while the other electrodes are grounded. The
control sample exhibits Gm degradation after hot carrier stress;
however the Gm of the CF4-pretreated sample shows little variation.
Clearly, the CF4-pretreated sample was better able to resist hot car-
rier stress than the control, perhaps because more fluorine was in-
corporated into the former.2,14 Figure 10 compares the transconduc-
tance degradation in more detail. This figure shows the degradation
of maximum transconductance. The transconductance degradation
of the control sample was around 3%. That of the 5 min sample was
only around 0.3%.
Figure 9. Degradation of the transconductance under constant current stress
for ͑a͒ the control sample and ͑b͒ the 5 min sample.
Conclusions
A thin tunneling oxide with superior electrical properties was
proposed and fabricated using CF4 plasma pretreatment. This
method increases the fluorination of simply fabricated oxides, in-
creases tunneling current, reduces leakage current, and increases re-
sistance against both stress-induced anomalous leakage and low
electric field ͑3-6 MV/cm͒ leakage currents. Furthermore, compar-
ing the MOSFETs demonstrated that CF4 plasma pretreatment could
sustain similar channel mobility and yield much higher resistance
against hot carrier stress. These excellent properties are very prom-
ising in fabricating low-voltage EEPROMs.
copy ͑AFM͒ was used to obtain a surface image to investigate sur-
face morphology. Figure 7 presents AFM images of the silicon sub-
strate surface of the ͑a͒ nontreated sample, ͑b͒ the sample treated
with CF4 for 3 min, and ͑c͒ the sample treated with CF4 for 5 min.
The root-mean-square ͑rms͒ value of surface morphology for each
sample was about 3-4 Å. Surface roughness does not significantly
differ among these samples; therefore, surface roughening caused by
the plasma treatment does not influence the differences among elec-
trical characteristics.
Figure 8a plots the drain current and transconductance vs. the
gate voltage of the control and the 5 min samples. A 10% decrease
was found in the drain current and transconductance of the
CF4-pretreated sample. The C-V data showed that the capacitance
decrement was also approximately 10%. That is, the degradation of
the on current is proportional to the decrease of capacitance. Ac-
cording to the TEM images, only the k value differs, perhaps further
indicating that the plasma pretreatment only slightly affects the
channel mobility of the MOSFETs. Furthermore, our fabricated ox-
ide ͑annealed in N2O ambient͒ shows degraded maximum transcon-
ductance but improved high-field mobility.17 These characteristics
are similar to those of the reoxidized-nitrided oxide.18 The reduction
of the maximum transconductance was due to electron trapping.
However, incorporating nitrogen can reduce acceptor-like interface
states and improve the high-field mobility. The drain current vs.
Acknowledgment
The authors thank the National Science Council of the Republic
of China, Taiwan, for financially supporting this research under con-
tract NSC 90-2215-E-009-095.
National Chiao Tung University assisted in meeting the publication costs
of this article.
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