Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxide-semiconductor devices

Article abstract of DOI:10.1063/1.3313946

We investigate the electrical properties of germanium-channel metal-oxide-semiconductor capacitors with an amorphous atomic-layer-deposited (ALD)-Al₂O₃ interlayer (IL) and higher- k ALD-TiO ₂ gate dielectric. An ALD-Al₂O₃ IL of ～1 nm thickness reduces the gate leakage current density at the otherwise low band-offset TiO₂ /Ge interface by six orders of magnitude at flatband. Devices with the thinnest Al₂O₃ IL exhibited a low capacitance equivalent thickness of 1.2 nm. The hysteresis of the capacitance-voltage curves was <10 mV for TiO₂/Al ₂O₃/Ge capacitors with different Al₂O ₃ thicknesses. We obtained a relatively low minimum density of interface states, Dit ～3× 10¹¹ cm^-2 eV ^-1, suggesting the potential of Al₂O₃ ILs for higher- k/Ge interface passivation.

Full text of DOI:10.1063/1.3313946

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Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxide-
semiconductor devices
Shankar Swaminathan, Michael Shandalov, Yasuhiro Oshima, and Paul C. McIntyre
Citation: Applied Physics Letters 96, 082904 (2010); doi: 10.1063/1.3313946
View online: http://dx.doi.org/10.1063/1.3313946
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/96/8?ver=pdfcov
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APPLIED PHYSICS LETTERS 96, 082904 ͑2010͒
Bilayer metal oxide gate insulators for scaled Ge-channel
metal-oxide-semiconductor devices
Shankar Swaminathan,1,a͒ Michael Shandalov,1 Yasuhiro Oshima,1,2 and Paul C. McIntyre1
1Department of Materials Science and Engineering, Stanford University, Stanford,
California 94305, USA
2Tokyo Electron U.S. Holdings Inc., Santa Clara, California 95054, USA
͑Received 17 December 2009; accepted 18 January 2010; published online 23 February 2010͒
We investigate the electrical properties of germanium-channel metal-oxide-semiconductor
capacitors with an amorphous atomic-layer-deposited ͑ALD͒-Al2O3 interlayer ͑IL͒ and higher-k
ALD-TiO2 gate dielectric. An ALD-Al2O3 IL of ϳ1 nm thickness reduces the gate leakage current
density at the otherwise low band-offset TiO2/Ge interface by six orders of magnitude at flatband.
Devices with the thinnest Al2O3 IL exhibited a low capacitance equivalent thickness of 1.2 nm. The
hysteresis of the capacitance-voltage curves was Ͻ10 mV for TiO2/Al2O3/Ge capacitors with
different Al2O3 thicknesses. We obtained a relatively low minimum density of interface states,
Dit ϳ3ϫ1011 cm−2 eV−1, suggesting the potential of Al2O3 ILs for higher-k/Ge interface
passivation. © 2010 American Institute of Physics. ͓doi:10.1063/1.3313946͔
Aggressive dimensional scaling of field-effect-transistors
͑FETs͒ has prompted interest in high mobility channel mate-
rials like germanium as an alternative to conventional Si-
based complementary-metal-oxide-semiconductor ͑MOS͒
devices. The difficulty of controlling the stoichiometry and
achieving thin physical thickness of GeO2 surface layers on
Ge motivates studies of high-k gate dielectrics on Ge.1 The
figure of merit, f, for direct tunneling-limited gate leakage
utes to remove the native oxide, blown dry with N2 and
transferred immediately to the high-vacuum loadlock of an
ALD chamber. ALD-Al2O3 ILs of different thicknesses ͑0.8,
1.2, and 3 nm͒ were deposited at 250 °C from 8, 12, and 30
cycles of a trimethyl aluminum ͑TMA͒/H2O process. Forty
cycles of ALD-TiO2 deposition ͑ϳ7 nm͒ were performed
using a tetrakisdimethylamino titanium/H2O process in situ
after Al2O3 deposition to fabricate p-Ge/Al2O3/TiO2 struc-
tures. These bilayer samples will be henceforth referred
to as 8 IL, 12 IL, and 30 IL for different Al2O3 IL thickness
͑8, 12, and 30 cycles͒, respectively. A control sample
current density of a gate stack is f =kͱ␾ where k is the
b
dielectric constant of the gate dielectric and ␾ is the tunnel
b
barrier height.2 Empirically, it is found that the inverse scal-
ing behavior of ␾ and permittivity makes dielectrics with
b
kϳ40 especially suitable for future scaling,3 prompting in-
terest in oxide gate insulators with k higher than that of HfO2
͑ϳ20͒, the state-of-the-art gate dielectric for Si-based MOS
devices. Also, an important requirement for the high-k gate
dielectric is a conduction band offset ͑CBO͒ to the semicon-
ductor channel in excess of 1 eV,4–6 to minimize gate leakage
current density. Titanium dioxide ͑TiO2͒ is a potential candi-
date for a higher-k dielectric with the bulk rutile crystalline
phase of TiO2 exhibiting k values as high as 60–80.4 How-
ever, TiO2 is predicted to possess zero CBO to Si or Ge
substrates.4 Therefore, there is a need to engineer ultrathin,
large band gap interlayers ͑ILs͒ between Ge FET channels
and higher-k oxides that would, by themselves, have low
band offsets to Ge.
Aluminum oxide is promising as an IL owing to its ex-
cellent thermal stability, large band gap ͑ϳ8.8 eV for the
␣-Al2O3 crystalline phase͒ and moderately-high dielectric
constant ͑kϳ8 in the bulk oxide4͒ to enable continued gate
capacitance scaling. Atomic layer deposition ͑ALD͒ is an
important tool to fabricate these proposed ILs because it of-
fers precise, monolayer-level thickness control.7 In this
study, we report on the application of in situ deposited
ALD-Al2O3 ILs between the Ge channel and the overlying
higher-k TiO2 layer.
Acceptor-doped ͑Ga, 2 ⍀ cm resistivity͒ Ge ͑100͒ sub-
FIG. 1. Cross-sectional TEM images of the bilayer stacked structure ͑a͒ 30
IL sample showing smooth, conformal deposition, and well-defined
Al2O3/Ge and TiO2 /Al2O3 interfaces ͑b͒ as-deposited 12 IL sample with
amorphous Al2O3 and TiO2 ͑c͒ Postannealed 30 IL sample with partially
crystalline TiO2 region highlighted within an oval.
strates were given a de-ionized ͑DI͒ H2O clean for five min-
a͒
Electronic mail: shanswam@stanford.edu.
0003-6951/2010/96͑8͒/082904/3/$30.00
96, 082904-1
© 2010 American Institute of Physics
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082904-2 Swaminathan et al.
Appl. Phys. Lett. 96, 082904 ͑2010͒
sistent with deposition rates for our TMA/H2O process
͑ϳ0.1 nm/cycle͒ are indicative of an ultrathin GeOx layer
of thickness less than the limit of resolution for measure-
ments of imperfect/disordered interfaces in the microscope
͑Ͻ2 Å layer thickness͒. The as-deposited Al2O3 and TiO2
films were amorphous, consistent with the low deposition
temperatures employed during ALD ͓Fig. 1͑b͒ for the 12 IL
sample͔. Thickness calibration of the TiO2 growth on the
Al2O3 starting surface revealed an enhanced deposition rate
of ϳ0.17 nm/cycle when compared to ALD-TiO2 on
DI-H2O cleaned Ge͑100͒ ͑0.1 nm/cycle for the CTRL
sample͒, suggestive of a smaller incubation regime for
ALD-TiO2 on Al2O3 than on the virgin Ge͑100͒ surface.
While the TiO2 layer was observed by TEM to be amorphous
in most electron-transparent regions after the FG anneal;
we observed a partially crystalline TiO2 region in one
postannealed 30 IL TEM sample, indicated by finely spaced
lattice fringes ͓Fig. 1͑c͔͒.
FIG. 2. ͑Color online͒ Gate leakage characteristics ͑J–V͒ of Pt-gated MOS
capacitors: CTRL, 8 IL, 12 IL, and 30 IL. The insertion of an Al2O3 IL at
the TiO2/Ge interface is beneficial in reducing the gate leakage by six orders
of magnitude at Vfb.
Figure 2 plots the leakage current density, J, as a func-
tion of the gate bias for the Pt-gated as-deposited bilayer
stack structures. The CTRL sample exhibited high leakage
current densities reaching the current compliance of the elec-
trometer ͑13 A/cm2 areal current density͒, as shown in Fig.
1. This is likely a consequence of the low CBO at the
TiO2/Ge interface. The introduction of an ultrathin Al2O3 IL
͑8 IL and 12 IL͒ reduces the leakage current significantly, by
approximately six orders of magnitude at the flatband volt-
age ͑Vfb͒. This is evidence of reduced tunneling of carriers
across the gate stack resulting from the increased CBO and
greater insulator thickness caused by the introduction of the
Al2O3 IL. Consistent with this observation, an experimental
value of 2.85 eV has been reported for the CBO for the
Al2O3/Ge interface.11 The gate leakage current density fur-
ther reduces to ϳ8ϫ10−8 A/cm2 at Vfb for the 30IL sample,
consistent with an exponential reduction in direct tunneling
current with the IL thickness. In comparison, it should be
pointed out that a Pt/30cyc ALD-Al2O3 ͑3 nm͒/Ge MOS ca-
pacitor exhibits a leakage current of 2.2ϫ10−4 A/cm2 at
Vfb, three orders of magnitude higher than the 30 IL sample
͑data not shown͒.
͑CTRL͒ was prepared by depositing 40 cycles of TiO2
͑ϳ4 nm͒ directly on the DI H2O cleaned-Ge substrate. Plati-
num gate metal of 50 nm thickness was deposited by e-beam
evaporation through a shadow mask, followed by deposition
of a 15 nm Ti/50 nm Al backside contact to reduce the con-
tact resistance. Postmetal forming gas annealing ͑FGA͒
͑5% H2/95% N2͒ was done on these capacitors for 30 min
at 350 °C. Parallel-mode, bidirectional, multifrequency
capacitance–voltage ͑C–V͒ sweeps on these MOS capacitors
were carried out using a HP4284A precision LCR meter.
Leakage current density–voltage ͑J–V͒ measurements used a
Keithley 230 programmable voltage source and electrometer.
The density of interface states, Dit, was extracted by low
temperature conductance measurements8 in a cryostation at
230 K to ensure factors such as thermal generation and weak
inversion response that interfere with Dit extraction at room
temperature were avoided.9,10
Cross-sectional transmission electron microscopy
͑XTEM͒ was done using Tecnai G2 microscope operating at
200 kV, to inspect the microstructure and thickness of the
samples. Figure 1͑a͒ shows an XTEM image of the 30 IL
bilayer stacked structure indicative of smooth, conformal
ALD of ϳ3 nm Al2O3 and ϳ7 nm TiO2 over a large sur-
face area, with well-defined, nearly-abrupt Al2O3/Ge and
TiO2/Al2O3 interfaces. The similarity in atomic numbers of
Ge and Al limits the ability of TEM to distinguish between
possible interfacial GeOx and Al2O3. However, the sharp na-
ture of the Al2O3/Ge interface and Al2O3 thicknesses con-
Figure 3 shows the bidirectional C–V sweeps of postan-
nealed stacks with different IL thickness from 1 to 100 kHz.
Multifrequency correction for the series resistance Rs was
done8 but an inconsistent value for Rs was obtained from the
three samples. The stack with the thinnest Al2O3 IL ͑8 IL͒
has a low capacitance equivalent thickness ͑CET͒ of 1.2 nm
͓Fig. 3͑a͔͒. This suggests that, with ultrathin deposited ILs,
FIG. 3. ͑Color online͒ Capacitance–voltage ͑C–V͒ characteristics of postannealed, Pt-gated MOS capacitors ͑a͒ 8 IL, ͑b͒ 12 IL, and ͑c͒ 30 IL. Sample 8 IL
shows a low capacitance-derived electrical thickness of 1.2 nm.
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082904-3 Swaminathan et al.
Appl. Phys. Lett. 96, 082904 ͑2010͒
FIG. 4. ͑Color online͒ Parallel conductance loss peaks ͑Gp͒ in the frequency domain for ͑a͒ as-deposited 12 IL sample ͑b͒ Postannealed 12 IL sample. ͑c͒ Dit
distribution in the p-type Ge band gap for as-deposited and postannealed 12 IL samples. Dit extraction was done by conductance measurements at 230 K.
subnanometer equivalent oxide thickness ͑EOT͒ can poten-
tially be reached if the substrate capacitance is taken into
consideration ͑beyond the scope of this study͒. The CETs for
the 12 IL and 30 IL stacks were observed to be 1.8 and 2.5
nm, respectively ͓Figs. 3͑b͒ and 3͑c͔͒. Assuming a k value of
7 for the ALD-Al2O3 layer, as determined in our previous
studies,12 k for TiO2 was calculated from the C–V plots and
TEM thickness calibration to be in the range of 32–35. This
k value is lower than the expected value of ϳ60 for bulk
rutile phase, as described earlier, and is attributed to the
largely amorphous nature of the ALD-TiO2. The hysteresis
for all three samples was observed to be Ͻ10 mV at Vfb,
indicative of low density of defects contributing to charge
trapping in the IL and the TiO2 film. The frequency disper-
sion in accumulation appears to decrease as the IL thickness
increases ͓Figs. 3͑a͒–3͑c͔͒. This suggests an increasing influ-
ence of traps in the dielectric layers on the measured C–V
characteristics as the Al2O3 IL is thinned down. The Vfb is
observed to shift toward positive gate bias as we increase the
IL thickness. This shift is consistent with a large negative
fixed charge incorporated in Al2O3/Ge stacks. As will be
reported elsewhere,12 the fixed charge for these
ALD-Al2O3/Ge stacks resides predominantly at the interface
rather than in the “bulk” of the Al2O3 layer.
We performed low temperature conductance measure-
ments on the 12 IL sample to extract the interface state den-
sity ͑Dit͒. The weak inversion response that gives rise to the
“bump” in the 1 kHz curve at room temperature ͓Fig. 3͑b͔͒ is
completely suppressed at 230 K ͑not shown͒. Figures 4͑a͒
and 4͑b͒ show the interface trap conductance Gp/␻, as a
function of the angular frequency ␻, in the depletion-to-weak
inversion surface potential regime for the as-deposited and
the post-FGA stacks, respectively. It can be seen that the
conductance in the post-FGA case is an order of magnitude
less for the as-deposited gate stack. Figure 4͑c͒ shows the Dit
distribution across a portion of the Ge band gap, extracted
from the conductance peaks for both the as-deposited and FG
annealed samples. It is evident that FGA reduces the Dit sig-
nificantly, both at midgap and approaching the band edges.
The minimum Dit of the postannealed samples was calcu-
lated to be 3ϫ1011 cm−2 eV−1. This indicates that the elec-
trical quality of the interface is comparable to that reported
for much thicker, stoichiometric GeO2 surface passivation
layers on Ge.10,13 The extent to which FGA promotes
H-induced passivation of dangling bonds is unclear. Ab initio
simulations and some experimental results suggest that Ge
dangling bond defects are negatively charged and are un-
likely to be passivated by atomic hydrogen, which also be-
haves an acceptor in Ge.14,15 Water-vapor based, oxidant-rich
ALD promotes residual –OH incorporation in as-deposited
oxide thin films. The interaction of atomic hydrogen with
–OH groups in the high-k oxide may cause monolayer-level
oxidation of the Ge ͑100͒ surface, producing GeO2-like
bonding which has been shown to provide a passive
interface.16
In summary, we have demonstrated that ultrathin Al2O3
ILs deposited by in situ ALD are effective in reducing gate
leakage at the low-CBO, TiO2/Ge interface. We were able to
scale down the CET of these devices to 1.2 nm, indicating
the capacitance scaling potential of such bilayer stacks. We
have also established that FGA is beneficial in lowering the
interface state density; annealed devices exhibited a mini-
mum Ditϳ3ϫ1011 cm−2 eV−1 near midgap. This study sug-
gests the potential of ALD-Al2O3 ILs as a route to achieving
interface passivation in higher-k/Ge MOS devices.
This research was supported by the MSD FCRP Focus
Center and Stanford INMP. S.S acknowledges financial sup-
port from the Yansouni Stanford Graduate Fellowship.
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