C O M M U N I C A T I O N S
Table 1. OTFT Data (Average of Eight Individual Devices) of the
Semiconductors under Different Substrate Deposition
Temperatures
We also fabricated OTFTs using these semiconductors on plastic
substrates with organic dielectric materials as insulators. Their
performance was the same as that with the silicon wafer substrates,
and these results will be reported elsewhere.
In conclusion, we have synthesized two novel organic semicon-
ductors based on thiophene-anthracene molecules, which show
remarkably high stability and very good electrical characteristics,
rendering these materials excellent OTFT semiconductors for
flexible electronics applications.
SC material
Tsub
(
°C)
µ
(cm2/Vs)
on/off
Vt (V)
SubTS (V/d)
DTAnt
23
60
80
90
100
20
60
80
100
120
120/80
0.037 ( 0.004 9.15 × 105 -13.6
2.40
1.32
1.75
2.27
1.94
2.56
2.17
2.56
2.46
2.77
1.87
0.048 ( 0.015 7.36 × 106
0.063 ( 0.006 8.76 × 105
0.035 ( 0.001 3.82 × 105
0.025 ( 0.001 2.92 × 105
-5.4
-6.3
-3.4
-3.0
DHTAnt
0.13 ( 0.016
0.31 ( 0.014
0.34 ( 0.011
0.48 ( 0.096
0.21 ( 0.023
0.50 ( 0.045
2.0 × 106 -21.8
2.5 × 107 -12.5
6.6 × 108 -13.6
5.5 × 107 -10.7
2.6 × 107 -11.4
2.8 × 107 -10.4
Acknowledgment. We thank our colleagues I. Malajovich, R.
J. Chesterfield, J. S. Meth, F. Gao, G. Nunes, L. K. Johnson, H. E.
Simmons, C. R. Fincher, G. B. Blanchet, P. F. Carcia, K. G. Sharp,
and K. L. Adams for useful discussions. We are grateful to K. D.
Dobbs for molecular modeling; R. S. McLean and D. J. Brill for
AFM; E. Y. Hung and C. M. Ruley for MS; S. A. Hill for NMR;
D. J. Redmond and R. V. Davidson for XRD; and R. A. Twaddell,
M. Y. Keating, and S. Ahooraei for TGA and DSC tests. H.M.
thanks Prof. Bao and Prof. Perepichka for valuable discussions.
Supporting Information Available: Details of experimental
procedures and additional data or spectra, information of OTFT device
fabrication (PDF), and X-ray crystal structure (CIF). This material is
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Figure 2. Characteristics of DHTAnt OFET devices (L ) 60 µm, W )
600 µm) fabricated at Tsub 80 °C. (Left) Plot of IDS vs VGS at various gate
voltages: Shelf life time test. (Right) Plots of IDS vs VGS at constant VDS
)
-40 V: Operation-lifetime test. (NB: Current data are absolute values.)
voids or cracks formed under elevated substrate temperature. The
origin of the cracks is likely due to different thermal expansion
coefficients between the semiconductor and the substrate. To further
investigate these morphology issues, we fabricated FETs using a
multiple-deposition method.10 By first evaporating to a 20-nm-
thickness film under a high substrate deposition temperature (120
°C), we were able to cover the majority of the surface, maintaining
the large grain size of the semiconductor. The cracks and voids
were then filled during a second 20-nm deposition at a lower
substrate deposition temperature (80 °C). By depositing the
semiconductor using this two-stage process, we were able to
increase the device mobility to 0.50 cm2/Vs with an on/off current
ratio of 107.
To test the device stability, we performed both shelf life tests
and continuous operation tests under ambient conditions. In the
shelf life test, the device mobility and on/off ratios were measured
periodically over a span of 15 months. Figure 2 (left) shows the IV
characteristics of the device before and after 15 months of storage,
over which time the performance of the device was largely
unchanged. The mobility varied from 0.35 to 0.42 cm2/Vs, and the
on/off ratio varied from 1.1 × 106 to 4.7 × 107. In the operation-
lifetime tests, the device was subjected to continuous operation
under a constant drain-source voltage VDS of -40 V and a
continuous sweeping of gate-source voltages VGS between +40
and -40 V. Figure 2 (right) plots the characteristics of IDS versus
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2960 double scans, showing little drop in performance. In all cases
there is no obvious hysteresis present in the IV curves. DTAnt-
based OTFT exhibited similar stability as DHTAnt.
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