Low-temperature dopant activation and its application to polycrystalline silicon thin film transistors

Article abstract of DOI:10.1063/1.118067

Low-temperature activation of dopants in amorphous silicon films was achieved by a new method and high-performance polycrystalline silicon thin film transistors were fabricated through its application. It was found that the dopants implanted into amorphous silicon were activated simultaneously with the crystallization of amorphous silicon. With the help of a thin nickel layer, the thermal budget for dopant activation and crystallization was considerably reduced, from 600°C (30 h) to 500°C (5 h). Even without plasma hydrogenation, the n-channel polycrystalline silicon thin film transistors fabricated at temperatures below 500°C showed a mobility of 120 cm²/V s, which is much higher than that of conventional devices fabricated at 600°C.

Full text of DOI:10.1063/1.118067

Lowtemperature dopant activation and its application to polycrystalline silicon thin film
transistors
SeokWoon Lee, TaeHyung Ihn, and SeungKi Joo
Citation: Applied Physics Letters 69, 380 (1996); doi: 10.1063/1.118067
View online: http://dx.doi.org/10.1063/1.118067
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/69/3?ver=pdfcov
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Low-temperature dopant activation and its application to polycrystalline
silicon thin film transistors
Seok-Woon Lee, Tae-Hyung Ihn, and Seung-Ki Joo
Department of Metallurgical Engineering, Seoul National University, San 56-1, Shillim-Dong, Kwanak-Ku,
Seoul 151-742, Korea
͑Received 20 February 1996; accepted for publication 17 May 1996͒
Low-temperature activation of dopants in amorphous silicon films was achieved by a new method
and high-performance polycrystalline silicon thin film transistors were fabricated through its
application. It was found that the dopants implanted into amorphous silicon were activated
simultaneously with the crystallization of amorphous silicon. With the help of a thin nickel layer, the
thermal budget for dopant activation and crystallization was considerably reduced, from 600 °C ͑30
h͒ to 500 °C ͑5 h͒. Even without plasma hydrogenation, the n-channel polycrystalline silicon thin
film transistors fabricated at temperatures below 500 °C showed a mobility of 120 cm2/V s, which
is much higher than that of conventional devices fabricated at 600 °C. © 1996 American Institute
of Physics. ͓S0003-6951͑96͒01229-6͔
Fabrication of polycrystalline silicon thin film transistors
͑poly-Si TFTs͒ on glass substrates has been attracting con-
siderable attention in the field of large-area, high-definition
liquid crystal displays. A major problem in commercial ap-
plication is that high-temperature processes are requisite for
the transformation of amorphous silicon (a-Si) into poly-Si
as well as the activation of dopants in poly-Si films, each of
which usually requires thermal annealings at around 600 °C
for several tens of hours1,2 even though the glass substrates
should be processed under 500 °C.
part, an application method for poly-Si TFTs is demonstrated
and the electronic device characteristics are compared with
those fabricated by a conventional method.
A thermally oxidized Si ͑100͒ wafer was used as a sub-
strate and an a-Si film of 1000 Å was deposited at 460 °C by
low-pressure chemical vapor deposition ͑LPCVD͒ using
disilane (Si2H6). The microstructure was characterized with
a scanning transmission electron microscope ͑STEM͒, Phil-
ips CM2000. The crystallinity, fraction of crystalline Si ͑c-
Si͒ to a-Si, was calculated from UV/visible ͑VIS͒ reflectance
spectroscopy as in Ref. 12.
The crystallization temperature of a-Si can be lowered
by the addition of some metals into a-Si,3–5 but this metal-
induced crystallization ͑MIC͒ phenomenon has not been ap-
plicable to the fabrication of electron devices because the
metal atoms incorporated into Si alter the semiconducting
properties of Si. For example, the crystallization temperature
of Al–Si is reported to be as low as 170 °C,6 but Al is an
acceptor-type dopant of Si. Besides, the crystallization is
more enhanced with the increase of metal content,7,8 so that
the problems related to the contamination becomes more se-
rious. Hence, it is of great significance to minimize the
amount of metal incorporation into Si while a lower crystal-
lization temperature is preferable. Recently, Liu and Fonash9
first showed that MIC can be applied to the fabrication of
poly-Si TFTs, where they tried to minimize the metal con-
tamination by depositing an ultrathin Pd layer under a-Si
films. Though they were able to reduce the crystallization
annealing time, the crystallization temperature was still kept
at 600 °C. More recently, a different crystallization phenom-
enon has been reported, where MIC could be extended later-
ally into the metal-free areas over 100 ␮m and this metal-
induced lateral crystallization ͑MILC͒ has been known to
take place only for Pd ͑Ref. 10͒ or Ni ͑Ref. 11͒ at tempera-
tures lower than 500 °C. MILC can provide large-grained
poly-Si films as well as low-temperature crystallization.
In this work, we developed a method that can reduce the
thermal budget necessary for activation of dopants in a-Si as
well as crystallization of a-Si. An ultrathin Ni layer is intro-
duced on top of a-Si films for this purpose. From the con-
tinual monitoring of the sheet resistance and of the crystal-
linity during heat treatment, the relationship between dopant
activation and crystallization is discussed. And in the last
P ions with an energy of 40 keV were implanted into
a-Si films and the ion dose was varied from 1ϫ1014 cmϪ2
to 3ϫ1015 cmϪ2. Figure 1 shows the variation of sheet re-
sistance for two different samples. A 5-Å-thick Ni layer was
deposited on top of a-Si after the implantation and then a 5 h
annealing at 500 °C was performed ͑Ni-MIC͒. In the case of
pure a-Si without a Ni layer, however, a 30 h annealing at
600 °C was necessary for the activation of dopants solid
phase crystallization ͑SPC͒. The crystallization of both a-Si
films was completed after these annealings and the further
annealing at each temperature turned out to have little effect
on the sheet resistance. Regardless of the sample structure,
FIG. 1. Variation of sheet resistance with P ion dose. For Ni-MIC, a 5-Å-
thick Ni layer was deposited after ion implantation and then the sample was
annealed at 500 °C for 5 h. For SPC, the annealing was done at 600 °C for
30 h after the ion implantation.
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137.149.200.5 On: Mon, 24 Nov 2014 23:18:01

shown in Fig. 3. In Fig. 3͑a͒, many needlelike Si crystals are
seen to form and be connected with each other although a
large portion of the matrix remains amorphous. In the case of
single crystalline Si, full activation of implanted ions re-
quires high-temperature annealing above 900 °C and only a
small portion of them is activated at temperatures around
600 °C. However, when the implanted region is amorphized,
the activation temperature is lowered because of the redistri-
bution of Si atoms during crystallization.13 Also in the case
of a-Si, the implanted P ions are activated as a-Si becomes
crystallized while those in the uncrystallized areas are not.
The conductivity of the P-doped c-Si is far lower than that of
the P-doped a-Si, so that electron current easily flows
through the interconnected Si crystals, rather than through
the a-Si matrix, when c-Si and a-Si are mixed in such a
random configuration as in Fig. 3͑a͒. This is why the sheet
resistance becomes reduced considerably when the crystal-
linity reaches a value of only 25% and almost saturated at a
crystallinity of 50%.
In Fig. 3͑b͒, it is surprising that the Si crystals have no
microtwins that are unavoidable in the poly-Si films crystal-
lized by conventional SPC. Additionally, a thin black-
colored layer is seen at the growing front of a needlelike Si
crystal. This layer looked distinguishable from Si, but was
not separable from c-Si even with a micro-microdiffraction
analysis, which infers that the crystal structure of this layer is
identical with that of Si. Additionally, the image in Fig. 3
closely coincides with the reports of Ref. 14 and Ref. 15, and
in Ref. 14, this layer was identified as NiSi2 of which the
lattice mismatch is only 0.4% with Si. When nickel reacts
with a-Si, the formation temperature of NiSi2 is known to be
around 400 °C.16 The preformed NiSi2 precipitates in an a-Si
matrix are responsible for a low-temperature crystallization
of a-Si because they provide suitable templates for the epi-
taxial nucleation of Si and the grain growth of Si is believed
to continue through the diffusion of Si atoms through a
NiSi2 layer.13 Therefore, the grain growth rate is reported to
be as high as ϳ5 Å/s at 517 °C,13 which is around two orders
of magnitude higher than that of intrinsic Si during solid-
phase epitaxy where the grain growth occurs through the
self-diffusion and rearrangements of Si atoms.17 Further-
more, it was also found that this kind of grain growth con-
tinues into the lateral Ni-free area over one hundred microns,
where the same microstructure in Fig. 3͑b͒ is still observed
and the growth rate was measured to be ϳ4 Å/s at 500 °C to
our surprise.18
FIG. 2. Variation of crystallinity and sheet resistance of Ni͑5 Å͒/a-Si͑1000
Å͒. Rapid thermal annealing was performed at 500 °C and the annealing
time was varied.
the sheet resistance decreased with the increase of the ion
dose, but the value of Ni-MIC was always lower than that of
SPC despite the lower annealing temperature and shorter an-
nealing time. Additionally, the thickness of a nickel layer
had no effect on the sheet resistance when the thickness was
varied from 2 to 50 Å.
The dependence of dopant activation on the crystalliza-
tion of P-doped Ni͑5 Å͒/a-Si͑1000 Å͒ is shown in Fig. 2.
The crystallization began in 40 min and was almost com-
pleted in 120 min, which was confirmed by UV/VIS reflec-
tance spectroscopy and STEM observation. The sheet resis-
tance began to decrease as the crystallinity became higher
than 10% and almost reached its minimum at a crystallinity
of 50%. In other words, the sheet resistance appeared to de-
pend on the crystallinity, but not correctly.
The microstructure of the films, the crystallinity of
which corresponds to 25% ͓a point marked ‘‘A’’ in Fig. 2͔, is
Figure 4 shows the fabrication steps of poly-Si TFTs
through the application of this method. A Ni film was depos-
ited on the whole surface of a TFT after the gate definition,
so that the a-Si films in the source/drain/gate areas are crys-
tallized by the above-mentioned method while only those in
the channel area are crystallized by MILC. Detailed experi-
mental conditions are as follows. A thermally oxidized Si
͑100͒ wafer was used as a substrate. After the definition of an
active island, a 1000-Å-thick SiO2 film for gate dielectric
was formed in an electron cyclotron resonance chamber
without substrate heating.11 The a-Si film ͑2000 Å͒ for gate
was also deposited by LPCVD. After the gate definition as in
Fig. 4͑a͒, P ions were implanted (5ϫ1015 cmϪ2, 40 keV͒
and a 20-Å-thick Ni layer was sputtered on the whole surface
FIG. 3. Transmission electron micrographs of the poly-Si films crystallized
by Ni-MIC: ͑a͒ Low-magnification, bright-field view of the poly-Si films
͑crystallinityϭ25%͒. ͑b͒ High-magnification view of a needlelike Si crystal.
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Appl. Phys. Lett., Vol. 69, No. 3, 15 July 1996 Lee, Ihn, and Joo 381
137.149.200.5 On: Mon, 24 Nov 2014 23:18:01

TABLE I. Device parameters of poly-Si TFTs. (W/Lϭ18 ␮m/6 ␮m͒. The
threshold voltage was defined at a normalized drain current (IDϫW/L) of
0.1 ␮A at VDSϭ1 V. The field-effect mobility was calculated in the linear
region at VDSϭ0.1 V. The maximum on/off current ratio was determined at
V
DSϭ1 V and VGSϭϪ10–25 V.
SPC
MILC
Parameter
͑600 °C, 30 h͒
͑500 °C, 25 h͒
Threshold voltage ͑V͒
5.5
1.00
30
1.2
0.58
Subthreshold slope ͑V/decade͒
Field-effect mobility (cm2/V s)
Maximum on/off current ratio
120
2ϫ107
6ϫ107
TFT. When we consider a high mobility of the small-grained
poly-Si films prepared by excimer laser annealing,21 mobility
depends largely on intragrain microdefects of poly-Si films.
Therefore, the high electron mobility of the MILC TFT can
be attributed to the high-quality poly-Si films in the channel
area as well as in the source/drain area, for the poly-Si films
crystallized by MIC or MILC have no microtwin defects,
unlike the SPC poly-Si films.
FIG. 4. Fabrication steps of MILC poly-Si TFTs: ͑a͒ Ion implantation for
source/drain and gate formation. ͑b͒ Deposition of a Ni layer ͑20 Å͒. ͑c͒
Annealing and electrode formation.
In conclusion, through the introduction of an ultrathin Ni
layer, low-temperature dopant activation as well as the crys-
tallization of a-Si is made possible. The dopants implanted
into a-Si appeared to be redistributed ͑activated͒ simulta-
neously with the redistribution of Si atoms in a-Si during
crystallization. With the help of this new method combined
with MILC, high performance poly-Si TFTs were success-
fully fabricated at temperatures below 500 °C. Therefore,
this new process is expected to enable the use of glass sub-
strates for LCDs application.
as in Fig. 4͑b͒. The thickness of a Ni layer was found to have
almost no effect on the device characteristics even when it
was varied from 2 to 50 Å.
Hence, all the processes were performed at temperatures
below 500 °C before the annealing and the annealing was
done at 500 °C for 25 h in H ambient. After the annealing,
͓
͔
2
the unreacted Ni on SiO2 was removed by wet chemical
etching. A 2000-Å-thick aluminum film was sputtered and
patterned for electrode formation as in Fig. 4͑c͒. The hydro-
gen plasma treatment was not performed.
This work has been supported by KOSEF through
RETCAM in Seoul National University.
For comparison, another poly-Si TFT was fabricated by
using conventional SPC. All the process conditions were
kept the same with the above process except that the crystal-
lization annealing was done at 600 °C for 30 h without using
a Ni layer.
Figure 5 shows the I–V characteristics of poly-Si TFTs
and key device parameters are summarized in Table I. The
mobility of the SPC TFT was ϳ30 cm2/V s, which is simi-
lar to that of other work.19,20 However, the MILC TFT shows
four times higher mobility (ϳ120 cm2/V s) and lower leak-
age current in the minus gate voltage region than the SPC
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