APPLIED PHYSICS LETTERS 95, 203112 ͑2009͒
Hai Liu, Domingo A. Ferrer, Fahmida Ferdousi, and Sanjay K. Banerjee
Microelectronics Research Center, R9950, The University of Texas at Austin, Austin, Texas 78758, USA
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Received 10 July 2009; accepted 14 September 2009; published online 18 November 2009͒
In this letter, we reported nanocrystal floating gate memory with Co–SiO core-shell nanocrystal
2
charge storage nodes. By using a water-in-oil microemulsion scheme, Co–SiO2 core-shell
nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate
without aggregation. The insulator shell also can help to increase the thermal stability of the
The flash memory market has increased very quickly
during the past decade. Nanocrystal ͑NC͒ floating gate flash
memory is considered to be one of the most promising can-
didates to replace conventional highly doped polysilicon
floating gate flash memory widely used in today’s commer-
cial market. Using discrete NCs embedded in a dielectric as
a floating gate to store charge, lateral charge migration in the
floating gate can be dramatically suppressed, making the de-
vice more robust against local defects, which can act as a
leakage path in the very thin tunneling oxide. Thus smaller
memory cell size, better programing/erasing characteristics,
rapidly injected in a three-neck flask containing 0.1 g of
tri-octylphosphine and 0.1 ml of oleic acid in refluxing DCB.
The temperature of the solution was lowered after 5 min and
the colloids were recovered using a gas-tight syringe. Sec-
ond, the Co NCs were coated with SiO2 by adding a 5 ml
aliquot of 0.5 mg ml− of synthesized colloids into a solu-
tion of 5 ml of Igepal CO-520 in 100 ml of cyclohexane.
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After this, a 0.6 ml solution of aqueous NH OH was added
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dropwise, for subsequent addition of 0.5 ml of tetraethyl
orthosilicate. This reaction proceeded for 48 h, after which
the NCs were recovered by employing a solvent/antisolvent
purification technique. This washing step included precipita-
tion with excess hexane and collection by centrifugation, fol-
lowed by redispersion in ethanol. Using the water-in-oil mi-
controlled shape and size, as shown in Fig. 2͑a͒, where the
first described by Tiwari et al., much work has been done in
Different materials, such as Si, Ge, SiGe, Ni, and Au,
have been studied to work as the charge storage nodes. To
achieve uniformly distributed NC matrix with high density,
diameter of cobalt core is about 3.4 nm and the SiO shell
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thickness is about 3.5 nm. When self-assembled, separated
by the insulating shell, the Co NCs can form a close pack
various NC deposition methods have been employed.
However, as the memory cell continuously scales down,
−2
with a density about ϳ0.8ϫ10 cm on the tunneling ox-
ide surface, as shown in Fig. 2͑b͒, without aggregation. In
our experiment, Co is more desirable as the core material
compared to its semiconductor counterpart, such as Si or Ge,
because metals have large work function and can be engi-
neered down to 1 nm without decreasing potential well depth
due to quantum confinement effects. Thus, continuous reduc-
tion of the shell thickness may yield ultrahigh density NC
matrix, which can potentially satisfy long term requirements
for nonvolatile memories as for ITRS 2007. After NCs were
Technology Roadmap for Semiconductors ͑ITRS͒ 2007,
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the memory cell size will reduce to ϳ1000 nm by 2020,
where only about ten NCs can be contained per memory cell.
For such small scale, it becomes increasing challenging to
synthesize suitable materials with uniform size and shape,
and assemble them into a well-ordered NC matrix. In this
letter, we present an approach to fabricate flash memory de-
vice with Co–SiO core-shell NCs as charge storage nodes
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in the floating gate, where the Co–SiO core-shell NCs are
2
deposited, the wafer was annealed in N at 500 °C for 10
2
synthesized by biochemical technique to achieve controlled
shape and size.
min. Then about 20 nm low-pressure chemical vapor depo-
The NC memory device with Co–SiO NC floating gate
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were fabricated on P-type silicon ͑100͒ substrate with the
resistivity about 1–10 ⍀ cm. A schematic structure is shown
in Fig. 1. After standard RCA clean and dilute 1:40 HF etch,
thermal SiO ͑ϳ2 nm͒ was grown on silicon substrate at
2
8
50 °C. Our solution-phase synthesis of colloidal NCs is
based on standard airless techniques on a Schlenk line.
First, cobalt NCs were fabricated by using a standard airless
technique. As precursor for cobalt, di-cobalt octacarbonyl
͓
CO ͑CO͒ ͔ was used. A solution of 0.54 g of CO ͑CO͒
2 8 2 8
diluted in 3 ml of anhydrous o-dichlorobenzene ͑DCB͒ was
FIG. 1. ͑Color online͒ Schematic cross section view of Co–SiO memory
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a͒Electronic mail: liuhai@mail:utexas.edu.
cell.
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003-6951/2009/95͑20͒/203112/3/$25.00
95, 203112-1
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Liu, Hai
