Rapid melt growth of germanium crystals with self-aligned microcrucibles on Si substrates

Article abstract of DOI:10.1149/1.1946368

A rapid melt growth method was developed to produce Ge crystals including Ge pillars, nanowires, and Ge-on-insulator. Amorphous Ge was deposited and patterned, then crystallized by melting and solidifying using Si substrates for seeding. Self-aligned SiO₂ microcrucibles were used to contain the Ge liquid during the crystallization anneal. The misfit defects were terminated within small regions around the seeding windows by a necking mechanism. Crystallization calculations showed that very high epitaxial growth velocity can be achieved when the temperature of Ge liquid is lower than but close to its melting point, while the random unseeded nucleation rate is very low in the same temperature range. High-quality Ge nanowires and Ge-on-insulator structures are produced with a simple and robust process. The rapid melt growth technique works very well with a variety of film thickness, including that of nanometer ultrathin structures. The surface smoothness obtained by Ge deposition is retained during crystallization and the film thickness is also controlled by deposition.

Full text of DOI:10.1149/1.1946368

G688
Journal of The Electrochemical Society, 152 ͑8͒ G688-G693 ͑2005͒
0013-4651/2005/152͑8͒/G688/6/$7.00 © The Electrochemical Society, Inc.
Rapid Melt Growth of Germanium Crystals with Self-Aligned
Microcrucibles on Si Substrates
,z
*
*
Yaocheng Liu, Michael D. Deal, and James D. Plummer
Center for Integrated Systems, Stanford University, Stanford, California 94305, USA
A rapid melt growth method was developed to produce Ge crystals including Ge pillars, nanowires, and Ge-on-insulator. Amor-
phous Ge was deposited and patterned, then crystallized by melting and solidifying using Si substrates for seeding. Self-aligned
SiO2 microcrucibles were used to contain the Ge liquid during the crystallization anneal. The misfit defects were terminated within
small regions around the seeding windows by a necking mechanism. Crystallization calculations showed that very high epitaxial
growth velocity can be achieved when the temperature of Ge liquid is lower than but close to its melting point, while the random
unseeded nucleation rate is very low in the same temperature range. High-quality Ge nanowires and Ge-on-insulator structures are
produced with a simple and robust process. The rapid melt growth technique works very well with a variety of film thickness,
including that of nanometer ultrathin structures. The surface smoothness obtained by Ge deposition is retained during crystalli-
zation and the film thickness is also controlled by deposition.
© 2005 The Electrochemical Society. ͓DOI: 10.1149/1.1946368͔ All rights reserved.
Manuscript submitted January 12, 2005; revised manuscript received March 8, 2005. Available electronically July 14, 2005.
Germanium is a promising semiconductor material due to its
Experimental Details
high carrier mobility and excellent optoelectronic properties.1-4
However, many process problems have to be solved with Ge. For
example, the mechanical properties of Ge are much worse than
those of Si. Ge wafers are brittle, which makes them hard to handle
during processing. They are also heavier than Si wafers of the same
dimensions. The thermal conductivity of Ge is lower than Si, which
might cause serious heat sink problems in integrated circuit prod-
ucts. In addition, the supply of Ge on Earth is limited. Ge-on-
insulator ͑GOI͒ substrates are considered a solution to these prob-
lems. With GOI on Si carrier wafers, Ge devices and circuits can be
manufactured with minimum modification to the current Si comple-
mentary metal-oxide-semiconductor ͑CMOS͒ fabrication facilities.
It also reduces the demand for Ge because only a thin Ge film is
needed for each wafer. GOI substrates also provide significant ad-
vantages over bulk Ge wafers in device properties such as lower
leakage currents for metal-oxide-semiconductor ͑MOS͒ transistors.
The main approaches that have been tried to make GOI usually
involve wafer bonding and layer separation.5 The thermal mismatch
between Si and Ge often causes serious problems in the annealing
steps involved in these approaches.
We have developed a technique, rapid melt growth, to fabricate
Ge crystals as well as GOI substrates by melting and crystallizing
deposited and patterned Ge, which is encapsulated with self-aligned
microcrucibles on Si substrates.6 A necking mechanism7,8 is used to
terminate the defects generated by lattice mismatch. Liquid-phase
epitaxy ͑LPE͒ was originally used to name the developed
technique.6 Because LPE usually refers to the method of growing
crystals epitaxially from diluted solutions, it is probably better to
call the technology developed in this work “rapid melt growth” to
avoid any confusion. Transmission electron microscopy ͑TEM͒,
scanning electron microscopy ͑SEM͒, atomic force microscopy
͑AFM͒, and Rutherford backscattering ͑RBS͒ were used to charac-
terize the GOI structures.
Two different kinds of structures were fabricated and used in the
experiments. The first were Ge pillars while the second were GOI
structures.
For the Ge pillars, a 0.5 ␮m thick amorphous Ge film was de-
posited onto a Si͑100͒ substrate in a low-pressure chemical vapor
deposition ͑LPCVD͒ furnace at 300°C, with a 20 sccm germane gas
flow under 400 mTorr pressure. Then lithography and anisotropic
reactive ion etch ͑RIE͒ were used to make Ge pillars with 0.5 ␮m
height and diameters ranging from submicrometer to nanometer
scales. Figure 1 shows a typical pillar structure with resist on top.
For the convenience of TEM observations, a large amount of
overetch was used to guarantee that the Ge/Si interface was ex-
posed. After the resist was stripped, a conformal low-temperature
SiO2 ͑LTO͒ layer was deposited to cover the pillars by LPCVD.
For the GOI structures, an insulator layer was first formed on a
Si͑100͒ substrate and patterned to open some seeding windows. The
insulator layer can be silicon dioxide, silicon nitride, or other mate-
rials. After opening the seeding widows, the wafers were cleaned
with an HF last cleaning procedure to make sure the native oxide in
the seeding windows was removed. Then the wafers were loaded
into an LPCVD furnace for amorphous Ge deposition. To enhance
the Ge coverage on the insulator layer, a very thin ͑Ͻ4 nm͒ Si layer
was first deposited in the LPCVD furnace. This was followed by the
Submicrometer Ge pillars and Ge nanowires were grown on Si
substrates using the developed technique. Nanowires grown with
this method have the significant advantage that they can be posi-
tioned at desired locations with precisely controlled growth direc-
tions.
GOI structures with very high quality were obtained with a
simple and robust rapid melt growth process. The GOI structures
can be easily integrated into a Si substrate and the process is com-
patible with a baseline CMOS fabrication.
Figure 1. TEM micrograph of a typical pillar with amorphous Ge on Si͑100͒
substrate. The photoresist ͑PR͒ as the RIE etch mask is also shown on top of
the pillar.
*
Electrochemical Society Active Member.
z E-mail: yaocheng@stanfordalumni.org
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Journal of The Electrochemical Society, 152 ͑8͒ G688-G693 ͑2005͒
G689
Figure 2. SEM micrograph of a Ge strip on silicon nitride with seeding
connection to Si substrate. The arrow shows the epitaxial growth direction
during rapid melt growth annealing.
nonselective Ge deposition. The amorphous Ge film was connected
to the Si substrate through the seeding windows. Next, the amor-
phous Ge film was patterned to the desired shapes by photolithog-
raphy and RIE. Figure 2 shows an example of patterned Ge film on
silicon nitride. As in the pillar experiment, a conformal LTO layer
was deposited to cover the patterned Ge.
Figure 4. TEM images of SPE Ge pillars.
The wafers with either pillars or GOI structures were then loaded
into a rapid thermal processing ͑RTP͒ chamber and heated up to
940°C to melt the Ge. In both cases, the LTO layer worked as a
microcrucible to hold the Ge liquid and prevent it from flowing
randomly. The ramp rate of the heating step was 100°C/s. The tem-
perature was held at 940°C for 1 s before the heating lamps were
turned off to let the wafers cool down naturally. The cooling rate
between 940 and 700°C was about 100°C/s. For comparison, a
solid-phase epitaxy ͑SPE͒ experiment was also carried out with Ge
pillar samples similar to those used in rapid melt growth. The SPE
annealing conditions were 425°C for 1 h.
After annealing, the LTO microcrucibles were removed by SiO2
etch using HF. SEM, AFM, and TEM were used to characterize the
Ge crystal quality. The etch pit density was counted to quantify the
defect density of the crystallized GOI. A 5:3:3:0.1 solution mixture
of HNO3:HF:CH3COOH:I2 was used for the selective defect etch
and an SEM was used in counting the number of defects.
Results and Discussion
Ge pillars.—Figure 3 shows some typical TEM micrographs of
the Ge pillars after the rapid melt growth anneal, while the SPE
pillars are shown in Fig. 4. The pillars in both figures are single
crystal with the same orientation as the Si͑100͒ substrate.
In all the crystallized pillars, some defects were generated at the
Ge/Si interface as expected due to the lattice mismatch between the
two crystals. However, because both Ge and Si are diamond struc-
ture materials, with slip systems of ͕111͖͗110͘, the threading dislo-
cations and stacking faults tend to lie in ͕111͖ planes.7,9 As we used
Si͑100͒ substrates and the TEM images were taken at ͓011͔ zone
axis, it can be clearly seen that the stacking faults make an angle of
54.7° to the ͑100͒ surface of the Si substrate ͑Fig. 3b͒. As a result, if
the aspect ratio of a Ge pillar is higher than 1.4 ͑tan͓54.7°͔͒, the
misfit defects can be terminated at the sidewalls of the pillar before
reaching the top of the pillar. This is similar to the necking mecha-
nism used in Czochralski growth. Some defects can also be termi-
nated when two of them meet each other, as shown in Fig. 3f. Figure
3 shows that the Ge crystals only have terminated misfit defects in
the bottom part while the top part is defect-free. However, many
To investigate the diffusion of Si from the seeding window to the
Ge film or pillars, a blanket 0.5 ␮m thick Ge film was deposited
onto a bare Si͑100͒ wafer. The same RTP anneal was carried out
with this sample without patterning the Ge film. RBS analysis was
used to detect the Si concentration in the crystallized Ge.
Figure 3. TEM micrographs of Ge pillars crystallized by rapid melt growth. ͑a͒ Ge pillar with 123 nm diameter. ͑b͒ Dark-field image of a 75 nm Ge pillar
showing defect necking at the bottom. ͑c͒ A Ge pillar with nanowire dimensions. ͑d͒ High-resolution image of the Ge pillar in ͑c͒. ͑e͒ Diffraction patterns
corresponding to the Ge pillar in ͑c͒. ͑f͒ High-resolution image showing two stacking faults terminated when meeting each other.
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G690
Journal of The Electrochemical Society, 152 ͑8͒ G688-G693 ͑2005͒
defects can be seen in the top parts of the SPE Ge pillars. The defect
density is very high for SPE pillars narrower than 100 nm ͑Fig. 4b͒.
With the rapid melt growth process, very high-quality Ge crystals
were produced even for pillars with diameters of nanometer scale
͑Fig. 3b and c͒. Therefore, the rapid melt growth method can be
used to make high-quality single-crystal Ge nanowires. This method
has the significant advantage that the nanowires can be precisely
located at desired positions with well-controlled growth directions.
Nucleation rate and growth velocity calculations.—In order to
use the rapid melt growth method to produce Ge films on an insu-
lator with high crystal quality, the epitaxial growth seeded by the Si
substrate has to propagate for a long enough distance before it is
interrupted by unseeded nucleation. Otherwise, the random un-
seeded nucleation would result in polycrystalline Ge films. In the
solidification of an undercooled liquid, both the growth velocity and
the nucleation rate change with temperature. They first increase with
undercooling due to an increase in the driving force for crystalliza-
tion, then reach some peak values at certain temperatures, and then
decrease as the temperature is further lowered because of slow
atomic motion. Generally the growth velocity peak value occurs at a
temperature higher than the temperature for the maximum nucle-
ation rate.10 Consequently, when the Ge liquid is cooled down from
above its melting point, it can be expected that there might exist a
process window in which the epitaxial growth would be dominant
over unseeded nucleation. This process window should be below,
but close to, the melting temperature.
Figure 5. Calculated growth velocity, homogeneous nucleation rate, and
heterogeneous nucleation rate as functions of temperature for a 0.1 ␮m
thick, 1 ␮m wide, and 10 ␮m long Ge liquid stripe on SiO2 and encapsu-
lated with SiO2 microcrucible.
⌬hF = 6.13 ϫ 10−20 J/at
␥
= 0.334 J/m2
SL
␯ = 1.27 ϫ 1012 Hz
0
⌬GЈ = 5.31 ϫ 10−20 J/at
M
Figure 5 shows the calculated homogeneous and heterogeneous
nucleation rates as well as the growth velocity at different tempera-
tures for an undercooled Ge liquid 0.1 ␮m thick, 1 ␮m wide, and
10 ␮m long with SiO2 both as the buried insulator and as the en-
capsulating layer. From this figure, a process window can be obvi-
ously seen near the melting temperature of Ge. The Ge growth ve-
locity is very fast. A single-crystal film can be easily obtained with
the Ge liquid under the RTP conditions such that the cooling rate is
100°C/s. The epitaxial growth can complete within several micro-
seconds, long before the temperature enters the region in which
unseeded nucleation is dominant. In the calculation, the contact
angle ␪ = 72° was estimated based on Turnbull’s solidification ex-
periments with undercooled Ge liquid on quartz or Pyrex glass
The homogeneous and heterogeneous nucleation rate can be cal-
culated with the following equations11-13
1/2
Ј
1
V2A/3
⌬GM
N
⌬G*
⌬G*
Ihom
=
␯ exp −
4␲͑r*͒2
exp −
ͩ ͪ
ͩ ͪ ͩ ͪ
0
kT
n* 3␲kT
kT
1/2
⌬G*het
Ј
V−A2/3
n*het
1
V2A/3
⌬GM
Ihet
=
␯ exp −
0
2␲͑r*͒2͑1 − cos ␪͒
ͩ ͪ
ͩ ͪ
kT
3␲kT
⌬G*het
ͩ ͪ
ϫexp −
kT
In the above equations, VA is the atomic volume, ␯ is the vibra-
tion frequency of atoms, and ⌬GЈ is the free energy of activation
0
surface.20 For simplicity, the same number was used for ⌬GЈ and
M
M
⌬GЉ , although they may have different values.14 The calculated
for the jumping of an atom across the liquid-nucleus interface. The
M
critical nucleus radius r* is determined by r* = 2␥SL/⌬GV, where
growth velocity is consistent in order of magnitude with the reported
measurement results for undercooled Ge liquid.16,17 The onset tem-
peratures for homogeneous and heterogeneous nucleation also agree
with the measured maximum undercooling.20,22
In fact, many experimental results have been reported in which
very large grains have been observed in the unseeded solidification
of undercooled Ge liquid.16,17,21,22 For example, if the undercooling
was less than 300°C prior to solidification, the grain sizes were
larger than 100 ␮m; if the undercooling was between 300 and
400°C, the grain sizes were in the range of 50-100 ␮m; when the
undercooling was more than 400°C, the grain sizes were around
10-20 ␮m.22
␥
is the interface energy between the liquid and the crystal, and
SL
⌬GV = ⌬gA/VA is the absolute value of free-energy change per vol-
ume corresponding to the liquid to crystal phase transition. The en-
ergy change per atom ⌬gA can be calculated by ⌬gA
Ϸ ͑⌬T/Tm͒⌬hF, where ⌬T is the amount of undercooling, Tm is the
melting temperature in Kelvin, and ⌬hF is the latent heat of fusion
per atom. N is the total number of atoms in the liquid, and n* and
n*het are the number of atoms in a critically sized nucleus for homo-
geneous nucleation and heterogeneous nucleation, respectively. The
free-energy changes are denoted as ⌬G* for homogeneous nucleus
formation and ⌬G*het for the heterogeneous case
Therefore, it is reasonable to expect that single-crystal Ge films
on an insulator can be produced with the rapid melt growth method.
⌬G*het = ⌬G*S͑␪͒, n*het = n*S͑␪͒
1
4
Ge-on-insulator structures.—The results of the GOI rapid melt
growth experiment confirm the existence of a process window. The
epitaxial growth started from the Ge/Si interface and propagated
laterally for a distance longer than 50 ␮m into the Ge liquid encap-
sulated by the LTO microcrucibles, yielding Ge single crystals with
large enough dimensions for device fabrication. Figure 6 shows
typical cross-sectional TEM photographs of the as-crystallized Ge
film. No obvious quality difference is observed between the Ge films
on silicon nitride and those on silicon dioxide.
As expected, a large number of defects are observed around the
Ge/Si interface. When the Ge was melted, it was inevitable that
interdiffusion would occur between Si and Ge. Some Si atoms were
dissolved in the Ge liquid. The Ge atoms injected into the Si sub-
2
where S͑␪͒ = ͑2 + cos ␪͒͑1 − cos ␪͒ and ␪ is the contact angle
between the heterogeneous nuclei and the crucible walls.
The growth velocity can be estimated with14
⌬GЉ
⌬gA
M
U = a ␯ exp −
1 − exp −
ͩ ͪ
ͩ ͪ
ͫ
ͬ
0
0
kT
kT
where a0 is the interatomic spacing and ⌬GЉ is the kinetic barrier
M
for the jumping of an atom across the liquid-crystal interface.
The values of the main thermodynamic parameters for Ge are
listed as follows15-20
Tm = 1211 K
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Journal of The Electrochemical Society, 152 ͑8͒ G688-G693 ͑2005͒
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Figure 7. TEM image showing defects extending upward with angles dif-
ferent from the expected 54.7° to the ͑100͒ surface of the Si substrate.
Ͻ5 ϫ 105 cm−2, which is very low considering that the whole rapid
melt growth process including Ge deposition, patterning, and crys-
tallization anneal was not optimized at all.
As the Ge liquid was held by the self-aligned LTO microcru-
cibles formed by conformal deposition, the surface roughness of the
crystallization films was determined by the Ge deposition process.
The surface morphology formed by deposition is retained during the
rapid melt growth. AFM was used to measure the surface roughness
of the as-deposited Ge films as well as that of the crystallized films.
The Ge films deposited by CVD on an insulator were not very
smooth but the surface roughness of the two measurements matched
with each other very well. The roughness of the as-deposited Ge
film was RMS = 1.98 nm. After rapid melt growth, the typical mea-
sured surface roughness was RMS = 2.11 nm. Smoother films could
be achieved by using sputter deposition. However, the carrier gas
trapped in the sputtered films often caused some problems during
rapid melt growth annealing. More work could be done to optimize
the Ge CVD technique to produce better smoothness. Deposition by
evaporation may be another option.
A concern one might have is the Si concentration in the crystal-
lized Ge films. Because the Ge was melted during rapid melt
growth, some diffusion of Si into the Ge liquid would be expected.
During the epitaxial growth in the cooling step, segregation of Si
between the crystal and liquid would occur, which would tend to
keep Si in the crystal and increase the purity of the remaining Ge
liquid. As the whole process is done in a very short time, it is very
difficult to do a precise quantitative calculation of the Si concentra-
tion in this complicated system. Figure 9 shows the Si profile mea-
sured by RBS. The RBS sample was made by the same rapid melt
growth anneal with a blanket Ge film on a bare Si substrate. It can
be obviously seen from the RBS results that there was some inter-
diffusion between Si and Ge. However, the Si concentration de-
creases very quickly in the Ge film when the location gets far away
from the interface. Based on this measurement, it can be expected
that the Si concentration in the crystallized Ge film on an insulator
should be below 1 atom % in the device regions micrometers away
from the seeding windows.
Figure 6. TEM micrographs of GOI made by rapid melt growth. ͑a͒ Typical
structure of the as-prepared GOI beyond seeding and necking regions. ͑b͒
Image of the seeding region. A high density of defects can be seen. ͑c͒
Lattice image of the Ge film. ͑d͒ The interface between Ge and buried insu-
lator ͑silicon nitride͒. ͑e͒ Diffraction pattern of the crystallized Ge film cor-
responding to ͑a͒.
strate caused the formation of SiGe solid solution with a gradient of
Ge concentration. A large number of defects were generated in this
SiGe region and some defects were generated in the Ge side. These
defects relaxed the misfit strain and hence the Ge crystal was re-
laxed. The key to obtaining defect-free Ge film on an insulator is the
action of the necking mechanism. Because the Ge film thickness is
very small compared to the lateral dimensions, the defects can reach
the top surface of the film and be terminated there within very short
lateral distances. But the defect extension along the horizontal di-
rections should also be considered. To prevent them from extending
too long into the film, the seeding connection between Ge and Si has
to be narrow or the Ge film can be patterned such that there is a
narrow necking zone before the epitaxial growth enters device re-
gions.
It has been reported that GOI MOS transistors with a ͑111͒ thin
Ge film may have enhanced channel mobility.23 By using a ͑111͒
The defect generation process was sometimes very complex and
the defects made angles different from 54.7° to the substrate surface
͑Fig. 7͒. No matter what angles they made, the defects could be
terminated by the top or side surface of the Ge film, by the sidewall
of the insulator step, or by the necking zone.
As can be seen from the TEM images ͑Fig. 6 and 7, the Ge
crystal quality is very high in the films beyond the seeding and
necking regions. No defects were detected.
Figure 8 shows an SEM image of a GOI structure after a defect
decoration etch with HNO3:HF:CH3COOH:I2 solution. Defect
necking along the horizontal direction can be seen in the image.
Quantitative counting was made with a large number of similar GOI
structures to find the defect density of the Ge films beyond the
seeding and necking regions. The defect density was found to be
Figure 8. SEM micrograph of a GOI structure after selective defect etch.
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Journal of The Electrochemical Society, 152 ͑8͒ G688-G693 ͑2005͒
Figure 9. Si and Ge concentrations measured by RBS. The “0” of the hori-
zontal axis represents the location of the Ge/Si interface. A positive distance
from the interface means the position is in the Ge side, while negative dis-
tance means Si side.
Figure 11. TEM image of high-quality GOI with 22 nm ultrathin Ge film
made by rapid melt growth.
Conclusions
Ge crystals including Ge pillars and Ge films on insulator were
grown with the rapid melt growth technique. Crystal growth velocity
and nucleation rate calculations show a large process window with
this technique even for GOI structures requiring long epitaxial
growth distances. In our experiments, Ge was deposited and pat-
terned on Si substrates and then heated to melt and cooled to crys-
tallize by rapid thermal processing. Self-aligned SiO2 microcru-
cibles were used to hold the Ge liquid. The epitaxial growth seeded
by Si substrates produced single-crystal Ge of very high quality. Ge
nanowires and GOI with ultrathin Ge films were successfully fabri-
cated, with their orientations controlled by the Si substrates. The
rapid melt growth method could also be applied to the fabrication of
other crystalline materials since the temperature dependence of
growth velocity and nucleation rate similar to that for Ge may also
exist for other materials.
oriented Si substrate, Ge͑111͒ films on an insulator were fabricated
with rapid melt growth ͑Fig. 10͒. The films grew along ͗110͘ direc-
tions laterally, with the top surface being a ͑111͒ plane. It was re-
ported that solid-phase epitaxy along ͗111͘ orientations for Si was
more defective than that along ͗100͘ or ͗110͘ orientations.24 We did
not observe this problem with the prepared ͑111͒ GOI. The reason
could be that the rapid melt growth was more defect-free than solid-
phase epitaxy or that the actual growth directions for the ͑111͒ GOI
were ͗110͘.
For modern advanced CMOS devices, ultrathin semiconductor
films are often desired to suppress short-channel effects.25 Crystal-
lization or recrystallization methods have the advantages of control-
ling the film thickness and surface roughness by deposition and
obtaining high crystal quality by annealing. However, it has been
found difficult to make high-quality ultrathin films by simple
SPE.26-28 When the film thickness is in the nanometer scale, the
LSPE growth cannot propagate for a long enough distance, and the
crystallized films have very high defect densities. In the first subsec-
tion of this section, it was mentioned that the SPE Ge pillars with
widths below 100 nm were very defective. This is consistent with
the observations reported for the SPE process. But in that subsec-
tion, we also demonstrated the high crystal quality achieved with
rapid melt growth even with Ge pillars of nanowire dimensions.
These results provide good reasons to believe that the rapid melt
growth method should work with ultrathin Ge films. Figure 11
shows the result of an ultrathin film rapid melt growth experiment.
The crystal quality of the 22 nm Ge thin film is as good as that
obtained with much thicker films.
Acknowledgments
This work was sponsored by DARPA Heterogeneous Integration
Program and MARCO Materials Structures and Devices Focus Cen-
ter. The authors feel grateful to Professor William D. Nix, Professor
Krishna C. Saraswat, and Dr. Peter G. Griffin of Stanford University
for helpful discussions. The RBS measurements done by Dr. Luncun
Wei at Charles Evans and Associates are acknowledged.
Stanford University assisted in meeting the publication costs of this
article.
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