Full text of DOI:10.1557/mrs2001.62

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bond pads, and formation of MEMS-to-
electronics interconnects.
Sandia National Laboratories has demon-
strated a modular poly-Si integrated MEMS
process that solves the topography prob-
lem by first etching a trench in the Si wafer
and then fabricating the MEMS device in
I
ntegrated MEMS
1
this trench. The trench is then filled with
Technologies
additional sacrificial-oxide depositions,
planarized by chemical–mechanical pol-
ishing (CMP), and sealed with a nitride
deposition. The electronics are then fabri-
cated on the pre-processed wafer using
a standard CMOS process. Contacts are
opened to poly-Si studs at the perimeter of
the trench prior to aluminum deposition
to form the MEMS–electronics interconnec-
tions. The electronics are then passivated
by an HF-resistant material for protection
during the sacrificial-oxide etching step
that releases the microstructures.
Andrea E. Franke, Tsu-Jae King,
and Roger T. Howe
Introduction
While microelectromechanical systems
MEMS) technology has made a substan-
Several issues must be considered in de-
veloping an integrated MEMS process. The
first is the process-temperature constraint
imposed by Al- or Cu-based integrated-
circuit (IC) metallization. Depending on
the particular interconnect metallurgy
used, the maximum post-metallization
temperature is in the range of 400–550ꢀC.
Asecond issue is the relatively thick MEMS
structural and sacrificial layers (2–10 ꢁm
thick), which create significant height
variations on the wafer surface. High-
resolution lithography, which is needed
for submicron CMOS (complementary
metal oxide semiconductor) transistors is
not possible on such rough surfaces. Elec-
trical interconnects between the MEMS
and electronics are also an important con-
sideration, since they should be of a
minimum length and made in a highly
conductive layer to minimize parasitic re-
sistance and capacitance. Finally, the pro-
tection of on-chip electronics from the
MEMS release etchant may be necessary.
For example, hydrofluoric acid (HF) is
typically used to remove sacrificial oxide
layers to release poly-Si microstructures.
Since the oxide layers and interconnect
metals employed in the electronic devices
are also etched in HF, they must be pro-
tected during the release etch.
(
tial impact over the past decade at the
device or component level, it has yet to
realize the “S” in its acronym, as complex
microsystems consisting of sensors and ac-
tuators integrated with sense, control, and
signal-processing electronics are still be-
yond the current state of the art. There are
several incentives to co-fabricate MEMS
devices and electronics on a single silicon
chip, which apply to applications such as
inertial sensors. The parasitic resistance
and capacitance associated with the inter-
connects between the MEMS devices and
electronics degrade electrical signal quality
and hence degrade system performance.
This problem is critical for thin-film, surface-
micromachined devices in which changes
in position are sensed as a small, capaci-
tively induced current. If the MEMS de-
vices can be co-fabricated with electronics
on a single chip, the parasitic resistance
and capacitance of these components can
be greatly reduced. The elimination of chip-
to-chip interconnections can also lead to
more reliable packages. This is especially
important for large arrays of MEMS de-
vices that require independent addressing
of each element, such as the micromirrors
in an optical cross-connect switch, for which
the monolithic integration of switching
electronics can reduce the number of off-
chip connections by orders of magnitude.
Depending on the integration strategy
that is adopted, the co-fabrication of mi-
crostructures and electronics on the same
substrate may provide significant overall
cost savings.
Another MEMS-first integration strategy
involves a different approach to planarize
the wafer after the deposition and pattern-
ing of the poly-Si MEMS layers. Rather
than etching a recessed well, the MEMS
film stack is formed on the wafer surface,
and then a layer is selectively grown by
epitaxy on the surrounding area to recover
a planar surface for electronics fabrica-
2
tion. Figure 1 is a scanning electron mi-
crograph of a 6-ꢁm-thick poly-Si lateral
accelerometer fabricated using this ap-
proach. The surface interconnects in Fig-
ure 1 are aluminum lines, which contact
poly-Si vertical feedthroughs at the pe-
rimeter of the MEMS area.
Interleaved MEMS/Electronics
Processes
By interleaving the MEMS and electronics
processing steps, the process designer has
maximum flexibility. With the exception
of the metallization, electronic device struc-
tures can tolerate temperatures as high as
900ꢀC without significant impact on their
characteristics. An attractive strategy for
poly-Si MEMS, therefore, is to postpone
the metallization steps until after the depo-
sition and annealing of the MEMS layers.
Interconnections between the electronics
and MEMS are relatively straightforward
in an interleaved process. However, the
process must allow for the topography of
the MEMS layers, which may require pla-
narization or relaxed layout design rules
for the metallization layers. In addition,
the electronics layers must be protected
during the release etch.
“MEMS-First”Modular Processes
By depositing, annealing, and pattern-
ing the MEMS layers before fabricating
the electronics, the thermal-budget con-
straint imposed by metallization is elimi-
nated for the MEMS process. This approach
is attractive for a MEMS technology that
requires high-temperature anneals for
residual-stress annealing or dopant acti-
vation, such as surface-micromachined
poly-Si technology. Integration issues
that must still be addressed are the topog-
raphy of the MEMS structures, passi-
vation of the electronics during the
release etch while allowing access to
This article surveys three approaches
to integrating MEMS with electronics by
means of co-fabrication in a single process
sequence: MEMS process steps completed
before the electronics process steps, MEMS
process steps interleaved with the electron-
ics process steps, and MEMS process steps
done after the electronics process steps.
In several cases, the initial demonstration
of an integrated MEMS technology has
used the flexible, interleaved approach.
Metal microstructures were fabricated as
gates of field-effect transistors in pioneer-
ing work at Westinghouse in the 1960s.3
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291

Integrated MEMS Technologies
make dense electrical interconnects between
the electronics and the SOI microstruc-
tures, which is solved by etching and re-
filling deep isolation trenches with an
insulating film prior to CMOS processing.
Figure 2 is a cross section showing a
7
trench-isolation process. The silicon
structures are etched by DRIE and then
released by HF etching after completion
of the CMOS process.
An integrated MEMS process has also
been developed using wafer bonding.8
First, trenches are etched in a handle
wafer and lined with silicon dioxide and
silicon nitride prior to bonding to a top
wafer. The top wafer is subsequently pol-
ished back to a p–n junction, defining the
MEMS layer thickness, after which the
electronics are fabricated. The MEMS
structures can then be defined either by
DRIE of the top silicon layer over the
buried trenches, or by anisotropic etching
from the back side of the handle wafer. In-
terconnection between the SOI structures
and the CMOS is possible through the
aligned bonding of a third, capping wafer,
on which metal lines are patterned.
Figure 1. Scanning electron micrograph of 6-ꢁm-thick poly-Si lateral accelerometer
fabricated using a “MEMS-first” integrated process. Courtesy of John Yasaitis, Analog
Devices Inc., Micromachined Products Div., Cambridge, MA.
2
“MEMS-Last”Modular Processes
Several groups have pursued a “MEMS-
last” integration strategy, using a variety
of MEMS processes. The primary chal-
lenge for the fabrication of MEMS devices
after completion of the electronics is the
thermal-budget limitation imposed by the
interconnect metallurgy. Surface topogra-
phy is not an issue because CMP is used
extensively in order to maintain planarity
for multiple levels of metallization in
modern CMOS processes. Passivation of
the electronics during the microstructure
release etch can be an issue if oxide or
interconnect metals are exposed in the
electronics areas.
Poly-Si microstructures were co-fabricated
poly structural layer are doped during
the same diffusion step. Following metal-
lization and passivation of the BiCMOS
circuits, which combine bipolar and
CMOS technologies, the epi-poly layer is
patterned by deep reactive ion etching
(DRIE), and the structures are released
with HF vapor.
The use of silicon-on-insulator (SOI)
substrates enables the fabrication of high-
aspect-ratio SCS microstructures formed
by DRIE of the silicon layer. The thickness
of the SOI-MEMS structures is equal to
the silicon layer thickness, which can be
10–100 ꢁm. The principal challenge is to
with a depletion-load n-channel MOS
(
NMOS) technology at Berkeley in 1984.4
In Analog Devices’ BiMEMS technology,
the metallization is done at the end of the
process. This process, used in production
since 1993, merges poly-Si microstructures
with a bipolar/MOS analog IC technology.5
Since only a single structural poly-Si layer
is used in this process, the topography
after completing the MEMS layers is not
too severe. The electronic devices have re-
laxed design rules, which enable them to
survive poly-Si stress-annealing tempera-
tures of approximately 900ꢀC. The poly-Si
structural layer in BiMEMS has a moder-
ate average tensile stress, as well as a sig-
nificant stress gradient through its thickness.
An alternative interleaved process strat-
egy uses an epitaxial growth process to
Considered here first are the CMOS
MEMS processes, which utilize the CMOS
layers to fabricate the microstructures.
6
form a thick poly-Si structural layer. First,
a bilayer of sacrificial oxide and poly-Si
is deposited and patterned in the MEMS
area of the wafer, under which the buried
diffusion layer used for bipolar transistors
can be patterned as a lower electrode
layer. Selective epitaxial silicon growth is
then performed, so that a thick (ꢀ10 ꢁm)
poly-Si layer known as epi-poly forms
over the poly-Si seed layer, while single-
crystal silicon (SCS) grows in the surround-
ing regions. The electronics are fabricated
in the SCS, and the gate poly-Si and epi-
Figure 2. Cross section of the silicon-on-insulator (SOI)–MEMS integrated process.7
292
MRS BULLETIN/APRIL 2001

Integrated MEMS Technologies
After completion of an unmodified CMOS
process, microstructures can be formed by
underetching regions of patterned thin
films, or by etching from the back side
of the wafer. Figure 3 shows a microma-
chined cantilever beam and the surround-
ing CMOS electronics that form part of an
chanical properties of these structures,
which consist of the CMOS metallization,
dielectrics, and SCS, are a consideration in
the design of the microsensor or actuator.
Cornell University’s SCREAM process
is another MEMS-last modular process that
uses DRIE to define the micromechanical
ture and a deep UV-hardened photoresist
is used for the sacrificial layers.12 The
polymer sacrificial layer can be etched in
an oxygen plasma so that the problem of
stiction (adhesion) or structural damage re-
sulting from drying after wet etching can
be avoided. Thick metal structures can be
fabricated by plating, as demonstrated in
a process using plated nickel as the struc-
tural layer with an aluminum/chromium
9
11
array of chemical sensors. This structure
structures. Oxide layers in the electronics
was fabricated by etching the substrate
using an anisotropic wet silicon etch such
are patterned and used as an etch mask
during DRIE of the SCS. Oxide and metal
“spacers” are then formed on the micro-
structure side walls by deposition and
anisotropic etching, and the microstruc-
tures are released by a timed, isotropic sili-
con etch that is masked by the side-wall
layers. Since only low-temperature proc-
esses, such as plasma-enhanced chemical
vapor deposition (CVD) and sputtering,
are used for microstructure fabrication,
there is no risk of damaging the electron-
ics. The significant topography that exists
after the silicon structures are defined makes
high-resolution patterning of the MEMS–
CMOS interconnects a challenge, however.
By using metal films deposited at low
temperatures as structural layers, surface
micromachining is feasible after CMOS
13
as KOH. The use of XeF vapor-phase
sacrificial layer. (For more on DMD™
technology, see the article by Hornbeck in
this issue.)
2
1
0
etching is attractive for post-CMOS
micromachining since it does not attack
many of the common CMOS layers such
as aluminum and oxides.
The development of a MEMS-last inte-
grated process that provides a surface-
micromachining technology with similar
capabilities to poly-Si MEMS foundry proc-
esses is a desirable goal. Over the past dec-
ade, MEMS designers have begun to exploit
the rich design possibilities in multi-
structural-layer surface-micromachining
foundry processes such as the Sandia
SUMMiT process (Sandia ultra-planar
The availability of RIE techniques has
increased the range of microstructures
that can be fabricated from unmodified
CMOS layers. The Application-Specific In-
tegrated MEMS Process Service (ASIMPS)
at Carnegie Mellon University uses the
metal layers in a standard CMOS process
as the etch mask for the silicon structural
10
14
layer. By leaving a thick SCS layer under-
neath the metallization stack, as shown in
cross section in Figure 4, residual stresses
in the thin films do not cause significant
warping of the released structures. The
microstructures are electrically connected
through the silicon layer unless the metal
lines are narrow enough that the silicon is
undercut during the DRIE step. The me-
multilevel MEMS technology). These
processes use low-pressure CVD (LPCVD)
poly-Si as the structural material, which
has excellent mechanical properties. Mi-
crohinges, pin joints, and linkages are con-
veniently made in these processes due to
the conformal deposition properties of the
LPCVD poly-Si structural layers.
fabrication. The Texas Instruments Digital
TM
Micromirror Device
is a commercial
product fabricated using a modular proc-
ess in which sputtered metals are used as
structural layers for the micromirror struc-
The use of poly-SiGe alloys as low-
temperature-processed structural mate-
rials has recently attracted the interest of
15–19
MEMS researchers.
LPCVD poly-SiGe
films, including pure poly-Ge, have me-
chanical properties comparable to those of
poly-Si, yet they can be processed at much
lower temperatures. In situ doped p-type
poly-SiGe films are particularly attractive
for a MEMS-last modular process since
annealing after deposition is not necessary
to achieve high conductivity and adequately
low residual stress and stress gradient.18
The issue of protecting the electronics dur-
ing the release etch is eliminated by using
poly-Ge rather than oxide as a sacrificial
material. This is because hydrogen perox-
ide (H O ), a highly selective etchant for
2
2
Ge, does not attack oxide, metal, poly-Si,
Figure 4. Cross section of a
microstructure fabricated using
the complementary metal oxide
semiconductor (CMOS) layers as the
etch mask in a “MEMS-last” modular
Figure 3. Cantilever-beam chemical sensor fabricated by selectively etching the silicon
substrate.9
10
approach foundry.
MRS BULLETIN/APRIL 2001
293

Integrated MEMS Technologies
or poly-SiGe with a Ge content of less
nificant area savings, this process mini-
mizes parasitic interconnect resistance
and capacitance. In order to enable more
sophisticated microstructures, additional
poly-Ge sacrificial and poly-SiGe struc-
tural layers can be deposited and patterned
without affecting the CMOS devices. As
with the other MEMS-last integrated
technologies, high-performance, low-cost
foundry CMOS wafers can serve as the
starting material for fabricating poly-SiGe
microsystems.
leaved BiMEMS poly-Si technology of
Analog Devices; the post-CMOS, substrate-
micromachining technology used by several
start-up companies; and the post-CMOS,
metal microstructure DMD technology of
Texas Instruments. Researchers have dem-
onstrated integrated processes for two
important classes of MEMS: (1) high-
aspect-ratio silicon or silicon/thin-film
composite microstructures and (2) poly-
SiGe surface-micromachined structures.
The former process is well suited to in-
ertial sensors requiring only a single struc-
tural layer, whereas the second process, if
extended to multiple structural layers, can
support complicated micromechanisms.
Given the wide variety of MEMS applica-
tions, it is likely that several integrated
processes will coexist, rather than a single
approach becoming dominant.
19
than 70%.
Figure 5 shows the cross section for a
modularly integrated poly-SiGe MEMS
process employing p-type poly-SiGe as the
structural material and poly-Ge as the sac-
rificial material, developed at the Univer-
sity of California—Berkeley.18 All MEMS
processing was performed at temperatures
ꢂ450ꢀC, so CMOS device characteristics
were not significantly affected. The circuits
were passivated with SiO and the Al pads
2
were exposed during the H O release.
2
2
In contrast to the “side-by-side” co-
fabrication of MEMS and electronics in a
MEMS-first modular process (see Figure 1),
poly-SiGe MEMS devices can be fabri-
cated directly on top of the electronics, as
shown in Figure 6. In addition to the sig-
Conclusions
Several approaches to co-fabricating
microstructures and electronic devices
on a single substrate have been briefly
reviewed. Commercial integrated MEMS–
electronics technologies include the inter-
Regardless of the approach taken, major
challenges remain for the successful ap-
plication of integrated MEMS–electronics
technologies. The back-end processes of
dicing, assembly, and encapsulation are
not standard, since the wafer contains re-
leased microstructures. Testing and calibra-
tion of MEMS present further challenges.
Although solutions to these issues have
been found for specific applications, gen-
eral solutions remain to be developed.
These issues will need to be addressed be-
fore MEMS can reach their full potential.
Figure 5. Cross section of a poly-SiGe microstructure fabricated on top of Al-metallized
CMOS.18
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