HfSiO4 dielectric layers deposited by ALD using HfCl4 and NH2(CH2)3Si(OC2H 5)3 precursors

Article abstract of DOI:10.1149/1.1803571

The physical and electrical properties of HfSiO₄ dielectric layers deposited by atomic layer deposition (ALD) are reported. The precursor chemistries used for deposition were HfCl₄/H₂O for HfO₂ and NH₂(CH₂)₃Si(OC ₂H₅)₃/O₃ for SiO₂. Two processes with HfCl₄:NH₂(CH₂) ₃Si(OC₂H₅)₃ precursor pulse ratios of 5:1 ( HfO₂-rich ) and 1:1 ( SiO₂- rich ) are investigated. Measurements with X-ray photoelectron spectroscopy and channeling Rutherford backscattering spectrometry show that these processes result in layers with Hf/(Hf + Si) ratios of 0.56 and 0.34-0.37, respectively. X-ray diffraction measurements showed formation of a HfO₂ cubic phase in HfO₂-rich layers starting at 850°C. In SiO₂-rich layers, no crystallization was detected up to 1100°C. Metal oxide semiconductor (MOS) capacitors with poly silicon electrodes were used for electrical characterization. The it-value of the SiO₂-rich layers was found to be 4.8-5.4 and that of the HfO₂-rich layers 12.5-15.1, both with an experimental error of 10%. The leakage currents of both types of layers were comparable to SiO₂ reference data and increased with polysilicon activation anneal. A high-resolution transmission electron microscopy study revealed phase segregation in thick SiO₂-rich layers. In HfO₂-rich layers, the phase segregation was less clear, but upon annealing, composition variations at the interfaces were detected. Given the experimental errors, no impact of phase segregation on the k-values of both types of layers could be detected. It is concluded that postdeposition annealing of HfSiO₄ layers for application as gate dielectrics applications in advanced complementary MOS technologies is essential to optimize stoichiometry and reduce leakage currents.

Full text of DOI:10.1149/1.1803571

C716
Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
0
013-4651/2004/151͑11͒/C716/7/$7.00 © The Electrochemical Society, Inc.
HfSiO Dielectric Layers Deposited by ALD Using HfCl4
4
and NH „CH … Si„OC H … Precursors
2
2 3
2
5 3
a,z
b,
b
b,
Z. M. Rittersma, F. Roozeboom, * M. A. Verheijen, J. G. M. van Berkum, *
b
b
c
c
c
T. Dao, J. H. M. Snijders, E. Vainonen-Ahlgren, E. Tois, M. Tuominen, and
c
S. Haukka,
a
Philips Research Leuven, 3001 Leuven, Belgium
Philips Research Laboratories, Eindhoven, 5656AA Eindhoven, The Netherlands
b
c
ASM Microchemistry, Limited, FIN-02630 Espoo, Finland
The physical and electrical properties of HfSiO4 dielectric layers deposited by atomic layer deposition ͑ALD͒ are reported. The
precursor chemistries used for deposition were HfCl /H O for HfO and NH (CH ) Si͑OC H ) /O for SiO . Two processes
4
2
2
2
2
3
2
5
3
3
2
with HfCl :NH (CH ) Si͑OC H ) precursor pulse ratios of 5:1 ͑‘‘HfO -rich’’͒ and 1:1 ͑‘‘SiO -rich’’͒ are investigated. Mea-
4
2
2
3
2
5
3
2
2
surements with X-ray photoelectron spectroscopy and channeling Rutherford backscattering spectrometry show that these pro-
cesses result in layers with Hf/͑Hf ϩ Si) ratios of 0.56 and 0.34-0.37, respectively. X-ray diffraction measurements showed
formation of a HfO cubic phase in HfO -rich layers starting at 850°C. In SiO -rich layers, no crystallization was detected up to
2
2
2
1100°C. Metal oxide semiconductor ͑MOS͒ capacitors with polysilicon electrodes were used for electrical characterization. The
k-value of the SiO -rich layers was found to be 4.8-5.4 and that of the HfO -rich layers 12.5-15.1, both with an experimental error
2
2
of 10%. The leakage currents of both types of layers were comparable to SiO2 reference data and increased with polysilicon
activation anneal. A high-resolution transmission electron microscopy study revealed phase segregation in thick SiO -rich layers.
2
In HfO -rich layers, the phase segregation was less clear, but upon annealing, composition variations at the interfaces were
2
detected. Given the experimental errors, no impact of phase segregation on the k-values of both types of layers could be detected.
It is concluded that postdeposition annealing of HfSiO layers for application as gate dielectrics applications in advanced comple-
4
mentary MOS technologies is essential to optimize stoichiometry and reduce leakage currents.
©
2004 The Electrochemical Society. ͓DOI: 10.1149/1.1803571͔ All rights reserved.
Manuscript submitted July 28, 2003; revised manuscript received May 26, 2004. Available electronically October 22, 2004.
For many years, silicon dioxide (SiO ) has been the gate dielec-
tric in complementary metal-oxide silicon ͑CMOS͒ technologies.
Scaling of the lateral dimensions of MOS-field-effect transistors
MOSFETs͒ in CMOS technologies has led to scaling of the gate
vantage of alloying HfO with SiO lies in the improved thermody-
2 2
2
namic stability of the dielectric layer, the increased conduction- and
valence-band offsets, and the higher carrier mobility in the inversion
1
6-19
͑
layer of MOSFETs.
Recently, promising MOSFET properties
dielectric thickness to values below 2 nm. When the gate length of
MOSFETs is scaled down, short channel effects ͑SCEs͒ become
dominant. Therefore, scaling of the gate dielectric thickness is re-
quired to maintain control of the gate voltage over the inversion
have also been obtained with HfSiON gate dielectrics. In particular,
it was shown that adding nitrogen to the silicate layer considerably
reduced the charge trapping properties and improved the threshold
2
0,21
voltage stability.
1
Both the chemistry and the deposition technique are crucial pa-
rameters for obtaining the desired layer composition of ternary
high-␬ gate dielectrics. An advanced technique to deposit high-␬d
dielectrics is atomic layer chemical vapor deposition ͑ALCVD™͒
charge at the Si/SiO interface. However, the SiO thickness reduc-
2
2
tion results in high leakage currents and degraded reliability. Incor-
porating nitrogen into SiO2 increases the relative permittivity ͑k-
value͒ from 3.9 for SiO to about 5-7 for nitrided SiO , i.e., SiON.
2
2
1
or atomic layer deposition ͑ALD͒. In this technique, the reactants
This means that at the same equivalent oxide thickness ͑EOT͒, the
are pulsed in separate sequences into the reaction chamber and the
saturating surface reactions are self-limited. Because of this, the
surface preparation is of utmost importance for the quality of ALD
leakage current through SiON layers is much smaller than through
2
SiO layers.
2
It is expected, however, that even SiON gate dielectrics will not
meet many requirements for aggressively scaled CMOS. Therefore,
dielectric layers with a high k-value, i.e., high-k dielectrics, are gain-
ing increasing attention for application as a gate dielectric in ad-
vanced CMOS technologies. Several alternative gate dielectric ma-
layers. Electrical and physical properties of ZrSiO layers deposited
4
22,23
by ALD were reported elsewhere.
In the present work, HfSiO4
layers deposited by ALD are investigated. The surface preparation
prior to HfSiO deposition was changed by one or more start pulses.
4
This procedure results in different starting surfaces, which may af-
3
4
terials such as Y O , Ta O , ZrO , and HfO have been investi-
2
3
2
5
2
2
fect the properties of the HfSiO layers. Reference HfO layers were
5
-7
4
2
gated. Also, rare-earth metal oxides like La O , PrO , and CeO
2
2
3
2
deposited using HfCl /H O chemistry on a 1 nm SiO layer. In the
have received considerable attention.8 However, finding a replace-
-10
4
2
2
following sections, the details of the layer deposition process and
experimental results from physical and electrical analysis are pre-
sented and discussed.
ment dielectric for SiO , which exhibits a sufficiently high k-value,
2
large band offsets, thermodynamic stability, high crystallization tem-
perature, low charge trapping properties, and good mobility proper-
ties appears challenging.11
Experimental
Hafnium-based dielectrics are expected to be thermodynamically
stable on Si. HfO has a k-value in the range of 18-22 and a bandgap
Hafnium-silicate (HfSiO ) layers were deposited with various
2
4
of about 6 eV, dependent on the deposition technique and applied
growth starting conditions, both on 1-3 ⍀ cm p-type or 1-8 ⍀ cm
n-type 4 in. single-crystal Si͑100͒ substrates in a flow-type F-450
ALCVD reactor located in a laboratory environment ͑clean room
class 100000͒ at ASM Microchemistry, Ltd., Finland. The deposi-
tion temperature was 300°C. Precursors used were trimethyl-
aluminum Al͑CH ) ͑TMA͒, HfCl , and 3-aminopropyltriethoxy si-
postdeposition anneals ͑PDAs͒.12 In order to improve the relatively
low crystallization temperature of around 600°C of pure HfO , al-
2
1
3-15
loying HfO with Al O and SiO has been proposed.
The ad-
2
2
3
2
3
3
4
*
Electrochemical Society Active Member.
E-mail: chris.rittersma@philips.com
d
z
ALCVD™ is a trademark of ASM International. Inc.
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Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
C717
lane NH (CH ) Si͑OC H ) ͑APTES͒. Ozone and water were
2
2
3
2
5 3
chosen as the oxygen sources. The composition of the layers was
varied by changing the HfCl :APTES pulse sequence ratio. Two
4
different processes were investigated
N ϫ ͑HfCl ϩ H O ϩ APTES ϩ O ͒ ͑SiO -rich͒
͓1͔
4
2
3
2
N ϫ ͓͑HfCl ϩ H O͒ ϫ 5 ϩ ͑APTES ϩ O ͔͒ ͑HfO -rich͒
4
2
3
2
͓2͔
where N is the number of cycles. Here, a precursor pulse followed
by an O - or H O pulse is referred to as one ͑pulse/purge͒ sequence.
3
2
The number of cycles N of the SiO -rich layers was 32, 85, or 170,
2
and for HfO -rich layers N was 3, 6, 11, or 20. The number of
2
sequences, defined as N ϫ 2 (SiO -rich͒ and N ϫ 6 (HfO -rich͒,
2
2
was hence 64, 170, and 340 for the SiO -rich layers, and 18, 36, 66,
2
and 120 for the HfO -rich layers, respectively. Prior to deposition, a
2
5
min 0.5% HF dip was followed by a 10 min O start pulse, or ten
3
cycles of TMA/H O. The latter results in a 0.8-0.9 nm thick Al O
2
2
3
film. Reference HfO layers with a thickness of 40 Å were deposited
2
on 8 in. p-type Si͑100͒ wafers with a thin ͑ϳ1 nm͒ oxide layer in a
Pulsar 2000 reactor ͑ASM Belgium͒.
Thickness measurements were done using a UV-visible spectro-
scopic reflectometer NanoSpec AFT/4000. The standard deviation
for the thicknesses of thin HfSiO layers was around 7% and for the
4
HfO layers smaller than 3%. For thicker layers (t Ͼ 20 nm͒, the
2
ox
Figure 1. Thickness of SiO -rich silicate layers for various starting condi-
tions. Average growth per pulse/purge sequence is 0.82-0.84 Å/pulse/purge
sequence.
standard deviation was in some cases 10-15%, most likely due to
CVD-like deposition as a result of inhomogeneous precursor flows
inside the chamber.22 X-ray diffraction ͑XRD͒ measurements were
done in the same system. Diffraction patterns were determined after
heating the samples for 30 min at a given temperature. The compo-
sition of the layers was determined by X-ray photoelectron spectros-
copy ͑XPS, Quantum 2000 from Phi͒ using Al K␣ radiation with a
2
tion variations. The ellipsometer thickness values were typically
2-20% higher than thickness values determined with HR-TEM.
2
Therefore, the growth rates determined here are likely overestimated
by the same percentage.
spot size of 100 ␮m . For comparison with the XPS results, chan-
neling Rutherford backscattering spectrometry ͑RBS͒ measurements
were taken from relatively thick ͑24-31 nm͒ layers which had re-
ceived various PDAs. A high-resolution transmission electron mi-
croscopy ͑HR-TEM, TECNAI F30ST͒ study was done to study the
HfSiO4 dielectrics and the HfSiO /silicon and HfSiO /polysilicon
Composition measurements.—The composition of the layers, in
particular the Hf/͑Hf ϩ Si) and the O/͑Hf ϩ Si) ratios, were deter-
4
4
interfaces as a function of annealing temperature.
MOS capacitors were fabricated by depositing 100 nm in situ
p-doped low-pressure chemical vapor deposited ͑LPCVD͒ polysili-
con and subsequent wet etching in HF/HNO . The deposition tem-
3
perature of the polysilicon layer was 590°C. Activation of the poly-
silicon and PDAs were done in a Mattson SHS1000 rapid thermal
anneal ͑RTA͒ system with a ramp rate of 50°C/s in flowing nitrogen.
A 30 ft H /N forming gas anneal ͑FGA͒ at 420°C was done after
2
2
patterning and polysilicon activation. The capacitor areas varied be-
2
tween 20 ϫ 20 and 200 ϫ 200 ␮m . Capacitance-voltage ͑C-V͒
measurements were done at 10 and 100 kHz using a HP4284A im-
pedance analyzer. For current-voltage ͑I-V͒ measurements, an
HP4155 analyzer was used. All electrical measurements were done
on a four-point probe station at constant temperature and under con-
stant N flow.
2
Results
Thickness and growth rates.—Figure 1 and 2 show the thickness
of the SiO -rich and HfO -rich HfSiO layers as a function of the
2
2
4
total number of ALD pulse/purge sequences and for different start-
ing conditions. Here the thickness was determined with an ellipsom-
eter ͑NanoSpec AFT/4000͒. The average growth rate per single
pulse/purge sequence was determined from the slope of the linear fit.
As-determined average growth rates of SiO -rich mixed layers range
2
from 0.84 Å/sequence ͑on Al O ) to 0.82 Å/sequence ͑with O start
2
3
3
pulse͒. For HfO -rich layers, growth rates of 2.25 Å/sequence ͑on
2
Al O ) and 2.1 Å/sequence ͑with O start pulse͒ were found. Esti-
2
3
3
Figure 2. Thickness of HfO -rich silicate layers for various starting condi-
2
mated errors in the growth rates are around 10%, considering non-
uniformity of the layer thickness and inaccuracies due to composi-
tions. Average growth per pulse/purge sequence is 2.26-2.42 Å/pulse/purge
sequence.
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C718
Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
Figure 3. RBS measurements of HfO -rich silicate layers with various
Figure 4. RBS measurements of SiO -rich silicate layers which received
2
2
PDAs.
as-indicated PDAs.
mined with XPS and with RBS measurements. Figure 3 and 4 show
values for SiO -rich layers͒. The increase of the O/͑Hf ϩ Si) ratio
2
RBS spectra of two HfSiO4 layers (HfO -rich and SiO -rich, re-
2
2
to 2.26 after a 1000°C, 1 s PDA in O might be due to reoxidation
2
spectively͒. The thicknesses of these two layers were 241 Ϯ 17 and
15 Ϯ 41 Å, respectively. Both layers were measured before and
after four different PDAs in the range 600-1000°C. The measure-
ments reveal that the Hf/͑Hf ϩ Si) ratio is not constant over the
entire layer thickness and that this ratio changes as a function of the
PDA temperature. In particular, the spectra show that as-deposited
of the HfSiO /Si interface. The fact that XPS does not confirm this
trend can be related to the depth resolution of about 9 nm, while the
layer is 6-7 times as thick.
4
3
Crystallization and interfaces (XRD,HR-TEM).—In Fig. 5,
XRD spectra of HfSiO layers are shown. The HfO -rich layer was
4
2
1
1 cycles ͓11 ϫ (5:1) (HfCl /H O:APTES/O )], t ϭ 16.2 nm,
layers exhibit an initially HfO -rich lower interface, whereas after
4 2 3 ox
2
and the SiO -rich layer 32 cycles ͓32 ϫ (1:1) (HfCl4 /
PDA it tends to become SiO -rich. Furthermore, simulations on
2
2
H O:APTES/O )], t ϭ 10.1 nm, both on native oxide.
these spectra indicate that after a PDA at 600°C or higher in O , the
2
3
ox
2
In the HfO -rich layer, the HfO -cubic phase is detected around
top layer becomes HfO -rich. Similar trends are observed for
2
2
2
8
50°C. In the SiO -rich layer, no crystallization could be identified
SiO -rich layers; however, here the variations become visible after
2
2
͑
with a detection limit of 1 mass %͒. The SiO -rich sample was
PDA at 800°C or higher.
2
measured up to three times and on different spots of the wafer and
after stabilizing the temperature at 1100°C for 30 min, but no peak
The RBS measurements were compared with XPS measurements
for a 90° incident angle of the beam. The penetration depth at this
angle is estimated to be 9 nm. In Table I a summary of both XPS
and RBS composition data is given for as-deposited layers and for
layers with different PDAs. As can be seen, for all PDA conditions
good agreement is obtained between the XPS and RBS data.
As can be seen from Table I, both SiO -rich and HfO -rich as-
could be detected. As compared to a binary HfO reference sample,
2
the HfSiO4 layers showed an improvement of the amorphous dielec-
tric phase by more than 250°C. Clearly, this can be attributed to the
presence of SiO in the layers.
2
A series of HR-TEM photographs of HfSiO layers are shown in
2
2
4
deposited layers appear to be oxygen-rich, i.e., the O/͑Hf ϩ Si) ra-
tio is higher than two. The RBS measurements show a tendency
toward more stoichiometric layers after annealing in the range of
Fig. 6. In the left column, the as-deposited layers are shown. In Fig.
6 ͑1͒ and ͑2͒, two HfO -rich layers are shown, and in Fig. 6 ͑3͒ and
2
͑4͒, two SiO -rich layers. In both cases, the layer was investigated
2
6
00-800°C for 10 s in O . After a 600°C, 10 s anneal, O/͑Hf ϩ Si͒
immediately after polysilicon deposition and after annealing the
polysilicon for 1 s at 1000°C. These photographs were taken at the
2
ϭ 2.08, and after a 800°C, 10 s anneal O/͑Hf ϩ Si͒ ϭ 2.00 ͑RBS
Table I. Summary of XPS and RBS composition data.
Pulse ratio
XPS
RBS
HfCl :APTES
PDA
Hf/͑Hf ϩ Si)
O/͑Hf ϩ Si)
Hf/͑Hf ϩ Si)
O/͑Hf ϩ Si)
4
1
:1
As-deposited
00°C, 10 s O2
00°C, 10 s O2
000°C, 0 s O2
As-deposited
00°C, 10 s O2
00°C, 10 s O2
000°C, 0 s O2
0.35
0.37
0.38
0.38
0.56
0.58
0.56
0.57
2.21
2.27
2.22
2.19
2.11
2.19
2.04
2.14
0.38
0.40
0.37
0.34
0.57
0.50
0.54
0.59
2.27
2.08
2.00
2.26
2.29
2.20
1.87
2.16
6
8
1
5
:1
6
8
1
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Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
C719
Figure 5. XRD results for HfO -rich and SiO -rich layers.
Figure 6. Series of HR-TEM photographs of HfSiO4 dielectric layers with
polysilicon electrodes: ͑1͒ HfO -rich layer ͑as deposited͒, t ϭ 94 Å, til
2
2
2
ox
ϭ 19 Å; ͑2͒ HfO -rich layer ͑1000°C RTA͒, t ϭ 107 Å, til ϭ 14 Å; ͑3͒
2
ox
SiO -rich layer ͑as deposited͒, t ϭ 143 Å, til ϭ 17 Å; and ͑4͒ SiO -rich
layer ͑1000°C RTA͒, tox ϭ 161 Å, til ϭ 15 Å.
2
2
ox
2
middle of large-area capacitors (1000 ϫ 1000 ␮m ͒, and therefore it
is assumed that lateral oxidation effects play no role. A clearly ob-
served difference between the HfO -rich and the SiO -rich layer is
2
2
the appearance of areas with lighter contrast in the latter. These
seem to become larger after anneal. In a number of previous publi-
cations, several authors have discussed the phase segregation in
ers, this increase is typically on the order of 3-6 Å. With the excep-
tion of layers grown with a H O start pulse, the dielectric/
2
24-26
polysilicon interface layer is less distinct for as-deposited SiO2-rich
HfSiO and ZrSiO dielectric layers.
The dielectric constant is
4
4
layers as compared to HfO -rich layers. However, its thickness in-
2
not only determined by the SiO /HfO ratio, but also by the shape
2
2
27,28
creases relatively more after polysilicon activation anneal than in the
and the size of phases inside the dielectric.
The observed phase
case of HfO -rich layers. After anneal, the thickness of this interface
2
segregation might therefore have consequences for the effective di-
electric constant of the layers.
A detailed overview of the changes in the thickness of the indi-
vidual layers is presented in Table II. A number of observations were
made. First of all, it is found that the overall thickness, i.e., the
dielectric thickness including both interface layers, increases after
was found to be as large as 18 Å.
The differences between as-deposited and annealed layers sug-
gest that the interface between ͑as-deposited͒ HfSiO dielectrics and
4
polysilicon are stable during the polysilicon deposition process itself
͑at 590°C͒, and that reactions take place during polysilicon activa-
tion temperatures at around 1000°C. Possibly, reactions already oc-
cur at lower temperature. A possible explanation for the interface
variations might be that the excess O present in the layers diffuses
toward the interfaces and oxidizes the polysilicon and the silicon
substrate. It remains unclear how the phosphorous doping in the
polysilicon affects the stability of the interface layer.
polysilicon anneal. Second, the lower interface of HfO -rich layers
2
grown with an O start pulse or on native oxide tends to become
3
more diffuse after anneal. That is, on top of a bright, SiO -rich
2
interface layer, a grayish layer with a slightly brighter contrast than
the bulk layer is observed. Furthermore, considerable changes at the
polysilicon/HfSiO interface were observed. An increase of the in-
4
terface layer between the dielectric and the polysilicon after anneal
Electrical characterization.—Figure 7 shows a number of C-V
is observed for all deposition starting conditions. For HfO -rich lay-
measurements of a SiO -rich HfSiO layer after various polysilicon
2
2
4
Table II. Comparison of HR-TEM thickness data with NanoSpec thickness data.
NanoSpec
Thickness ͑TEM͒a
IL ͑TEM͒b
Layer ID
Startpulse
Pulse ratio
As-deposited ͑Å͒
As-deposited ͑Å͒
1000°C ͑Å͒
As-deposited ͑Å͒
1000°C ͑Å͒
B1គD02
B1គD11
B1គD18
B2គD04
B2គD06
B2គD07
B2គD10
Native oxide
5:1
5:1
5:1
1:1
1:1
1:1
1:1
62
159
52
59
66
48
94
47
49
75
51
107
39
60
80
9
19
17
14
12
17
11
8
14
16
12
11
15
14
H O pulse
2
Al O
2
3
O pulse
3
H O pulse
2
Native oxide
142
103
143
78
161
81
Al O
2
3
a
Total thickness of the dielectric, including top and bottom interface layers.
Thickness of the bright bottom interface layer.
b
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C720
Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
Figure 7. C-V characteristics of SiO -rich HfSiO ͑64 cycles 1:1 with O3
2
4
start pulse͒ for various polysilicon anneals ͑silicate layer is as-deposited͒.
EOTs range from 38.3 ͑as-deposited͒ to 40.4 Å ͑1070°C spike anneal͒.
Figure 9. C-V measurements of HfO -rich layer on Al O start surface,
2
2
3
including reference HfO with polysilicon after 900°C activation anneal.
2
activation anneals. These SiO -rich layers received no PDA prior to
2
polysilicon deposition. The equivalent oxide thickness ͑EOT͒ of this
layer varied between 38.3 ͑as-deposited͒ and 34.6 Å ͑1000°C, 1 s
RTP͒. After a 1070°C, 0 s RTA step, the capacitor appears to break
down; the observed increase of the EOT is most likely due to inter-
face oxide growth. The EOT values were obtained using a MOS
C-V simulation program, taking into account quantum-mechanical
corrections and polysilicon depletion effects.29 For the four shown
measurements, the flatband voltage VFB changed from Ϫ580 ͑as
deposited͒, Ϫ554 ͑900°C͒, and Ϫ469 ͑1000°C͒, to Ϫ481 mV
͑1070°C͒. Assuming this shift is completely due to fixed charge Qfix
located at the interfaces, this corresponds to an increase from 3.5 to
5.8 ϫ 10 cm in the range ‘‘as-deposited, 1000°C.’’ The leakage
currents of equally sized capacitors is shown in Fig. 8. In the range
1
1
Ϫ2
as-deposited to 1000°C RTA, the current density at ͉VFB Ϫ 1͉ in-
Figure 8. I-V characteristics of SiO -rich HfSiO layers for various poly-
Figure 10. I-V measurements of HfO2-rich HfSiO4 layer on Al2O3 start
2
4
silicon anneals ͑same layer as in Fig. 7͒.
surface, including reference data of 4 nm HfO2 .
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Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
C721
Figure 11. EOT of silicate layers vs. gate dielectric thickness. EOT vs. oxide
Figure 12. As-determined k-values of HfSiO layers vs. Hf/͑Hf ϩ Si) ratio.
thickness ͑NanoSpec data͒. The k-value for SiO -rich layers equals 4.8; for
4
2
2
3
Data of ALD ZrSiO layers from previous work included.
HfO -rich layers the k-value is 15.1.
4
2
where t is physical thickness of the layer and the subscripts refer
to the ͑lower͒ interface layer ͑IL͒ and the high-␬ dielectric ͑d͒. In
creases from 3.1 ϫ 10Ϫ8 to 1.4 ϫ 10Ϫ6 A cmϪ2, i.e., two orders of
magnitude. After anneal at 1070°C, the current density increases
another two orders of magnitude.
Fig. 11, the EOT of the HfSiO layers is plotted vs. the thickness
4
of the layers ͑ellipsometer data, as-deposited polysilicon͒. The as-
In Fig. 9 and 10, C-V- and I-V measurements of a 52 Å thick
determined k-values of SiO -rich layers are k ϭ 5.5 (O3 start
2
HfO -rich layer grown on Al O are shown. Measurements of 1 nm
2
2
3
pulse, not shown͒ and k ϭ 4.8 (Al O start surface͒, and of HfO -
2
3
2
SiO /4 nm HfO with no PDA and the same polysilicon electrode
2
2
rich layers with identical start conditions k ϭ 12.3 and 15.1,
respectively.
are included as reference. The thinnest EOT of this HfO layer was
2
27.9 Å after 1000°C, 1 s activation anneal and subsequent 420°C, 20
min N /H anneal. The flatband voltage V of this layer shifted
2
2
FB
from Ϫ582 to Ϫ666 mV ͑with increasing RTA temperature͒, i.e.,
shifted by 336-260 mV from the ideal VFB . The VFB of the reference
HfO was shifted by 392 mV (V ϭ Ϫ485 mV͒. It was found that
2
FB
the VFB of this HfO layer could be shifted 100 mV toward the ideal
2
value with a 600°C, 10 s PDA in O , without an increase in the
2
EOT. Annealing a 75 Å thick HfO -rich mixed layer at higher tem-
2
perature, i.e., in the range 800-1000°C for 10 s in O , showed that
2
the VFB , with as-deposited polysilicon, could be improved from
Ϫ603 mV ͑as-deposited͒ to Ϫ722 mV ͑1000°C, 1 s O ), however, at
2
the expense of a considerable increase in EOT. The hysteresis, mea-
sured at VFB , in the layers was typically on the order of 5-15 mV for
thin layers ͑52 Å HfO -rich on Al O ) and up to 138 mV for thick
2
2
3
layers ͑B2គD10, tox ϭ 103 Å͒, with no clear trend difference be-
tween SiO -rich and HfO -rich layers. The EOT values of all inves-
2
2
tigated as-deposited HfSiO4 layers without polysilicon activation
varied between 38 and 230 Å for SiO -rich layers and between
2
3
2 and 164 Å for HfO -rich layers. After activation anneals, EOT
2
values decreased typically by 5-15% of the as-deposited value,
while the total dielectric thickness increased ͑see HR-TEM results,
Table II͒.
The k-values of the layers were found using a linear fit of EOT
vs. physical thickness
␬SiO2
␬IL
␬SiO2
Figure 13. Leakage current densities at
SiO -rich and HfO -rich layers͒.
͉VFB Ϫ 1͉ as function of EOT ͑both
EOT ϭ
tIL
ϩ
td
͓3͔
␬d
2
2
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C722
Journal of The Electrochemical Society, 151 ͑11͒ C716-C722 ͑2004͒
According to Table II, the thickness of the layers as found with
neling is the dominating leakage current mechanism. Therefore, op-
NanoSpec is overestimated by roughly 10% as compared to HR-
TEM, so that the k-values given here are possibly overestimated by
the same percentage. The possible k-value variation as a function of
the annealing temperature and the phase segregation as discussed
previously could not be accurately determined, mainly because of
the uncertainty in the physical thickness of the layers after anneal-
ing. Considering errors in fitting the C-V data and variation in the
thickness and composition, the estimated overall error in the given
k-values is around 10%.
timizing the stoichiometry of the HfSiO layers without compromis-
ing the EOT seems crucial for improving both the thermodynamic
4
and the electrical properties of ALD HfSiO layers deposited using
4
this chemistry.
Acknowledgments
The authors thank Jan Verhoeven and Jaap Snijder ͑Philips͒ for
their assistance in fabricating the MOS capacitors, David Massoubre
for C-V and I-V measurements, Emile Naburgh ͑Philips͒ for XRD
measurements, Yde Tamminga and Ad Hendriks ͑Philips͒ for their
assistance with RBS and XPS measurements, and Jan Willem Maes
It has been suggested in the past that the k-values of HfO /SiO
2
2
3
0
vary superlinearly as a function of the Hf:Si composition ratio. In
Fig. 12, the k-values of HfSiO4 are plotted vs. the Hf/͑Hf ϩ Si)
composition ratio ͑RBS data͒. In this figure, two data points of ALD
͑
ASM͒ for depositing the HfO reference wafers.
2
23
ZrO /SiO layers have been included. Clearly, we observe a sub-
Philips Research Leuven assisted in meeting the publication costs of this
article.
2
2
linear scaling behavior of the k-value as function of the composition.
Figure 13 shows that the leakage currents measured at VFB
Ϫ 1 are higher than the SiO reference. This indicates that both
͉
References
͉
2
1
2
. P. M. Solomon, Annu. Rev. Mater. Sci., 2000, 30:681-97.
. M. L. Green, E. P. Gusev, R. Degraeve, and E. L. Garfunkel, J. Appl. Phys., 90,
types of HfSiO layers are rather poor dielectrics. The high leakage
4
currents might be due to the intrinsic roughness in the silicon sub-
strates ͑see HR-TEM in Fig. 6͒ or abundant bulk or interface de-
fects. Both types of defects result in defect-assisted tunneling
through the bulk of the layers. This was investigated by measuring
the I-V characteristics in the range 25-150°C. An increase of the
leakage current at higher substrate temperature could indicate the
presence of shallow defects, which are thermally activated. Here it
was found that an increase of the temperature had only a minor
effect ͑Ͻ0.5 order of magnitude͒ on the leakage current through thin
layers, whereas one to two orders of leakage current increase could
be observed for thicker layers. This would indicate direct tunneling
through thinner layers and defect-assisted tunneling through the
thicker layers.
2
057 ͑2001͒.
3. A. Dimoulas, G. Vellianitis, A. Travlos, V. Ioannou-Sougleridis, and A. G. Nas-
siopolou, J. Appl. Phys., 92, 426 ͑2002͒.
. K. M. A. Salam, H. Konishi, H. Fukuda, and S. Nomura, Proc. IWGI ͑2001͒.
. M. Copel, M. Gribelyuk, and E. Gusev, Appl. Phys. Lett., 76, 436 ͑2000͒.
. M. Gutowski, J. E. Jaffe, C. L. Liu, M. Stoker, R. I. Hegde, R. S. Rai, and P. J.
Tobin, Appl. Phys. Lett., 80, 1897 ͑2002͒.
7. Y. Kim et al., Tech. Dig. - Int. Electron Devices Meet., 2001, 485.
. J.-P. Maria, D. Wicaksana, A. I. Kingon, B. Busch, H. Schulte, E. Garfunkel, and T.
Gustafsson, J. Appl. Phys., 90, 3476 ͑2001͒.
. H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, Tech. Dig. - Int.
Electron Devices Meet., 2000, 653.
4
5
6
8
9
10. L. P. Wang, B. Y. Tang, N. Huang, X. B. Tian, and P. K. Chu, Mater. Sci. Eng., A,
08, 176 ͑2001͒.
1. G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys., 89, 5243 ͑2001͒.
3
1
1
1
1
1
2. P. W. Peacock and J. Robertson, J. Appl. Phys., 92, 4712 ͑2002͒.
3. A. Kawamoto, Ph.D. Dissertation, Stanford University, Stanford, CA ͑2001͒.
4. D. A. Neumayer and E. Cartier, J. Appl. Phys., 90, 1801 ͑2001͒.
5. W. Zhu, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson, and T.
Furakawa, Tech. Dig. - Int. Electron Devices Meet., 2001, 463.
16. G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys., 87, 484 ͑2000͒.
17. E. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn-Schmidt, and T. Zabel, J. Appl.
Phys., 90, 6466 ͑2001͒.
8. B. C. Hendrix, A. S. Borovik, C. Xu, J. F. Roeder, T. H. Baum, M. J. Bevan, M. R.
Visokay, J. J. Chambers, A. L. P. Rotondaro, H. Bu, and L. Colombo, Appl. Phys.
Lett., 80, 2362 ͑2002͒.
9. M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, J. Appl. Phys., 90, 4587 ͑2001͒.
0. A. L. P. Rotondaro, Proc. IEEE VLSI 2002 Symposium.
1. S. Inumiya, Proc. IEEE VLSI 2003 Symposium.
Conclusions
The physical and electrical properties of HfSiO layers deposited
4
by ALD using HfCl and APTES as precursors were reported. An
4
HfCl :APTES ALD pulse ratio of 1:1 resulted in a SiO -rich HfSiO
4
2
4
dielectric layer with a Hf/͑Hf ϩ Si) ratio of around 0.36. The aver-
age deposition rate of this type of HfSiO4 layer is 0.82-0.84
1
Å/sequence. A HfCl :APTES ALD-pulse ratio of 5:1 resulted in a
4
1
2
2
HfO -rich layer with a Hf/͑Hf ϩ Si) ratio of 0.56 and an average
2
deposition rate of 2.25-2.42 Å/sequence. In both types of layers,
roughly 10% excess oxygen was found (O/͑Hf ϩ Si) ϳ 2.2). In the
first, no crystallization was found up to 1100°C, and in the latter the
22. E. Vainonen-Ahlgren, E. Tois, T. Ahlgren, L. Kriachtchev, J. Marles, S. Haukka,
and M. Tuominen, Comput. Mater. Sci., 27, 65 ͑2003͒.
2
3. Z. M. Rittersma, E. Naburgh, T. Dao, A. H. C. Hendriks, W. F. A. Besling, E. Tois,
E. Vainonen-Ahlgren, M. Tuominen, and S. Haukka, Electrochem. Solid-State Lett.,
6, F21 ͑2003͒.
4. H. Kim, J. Appl. Phys., 92, 5094 ͑2002͒.
5. S. Stemmer, Y. Yu, B. Foran, P. S. Lysaght, S. K. Streiffer, P. Fuoss, and S. Seifert,
Appl. Phys. Lett., 83, 3141 ͑2003͒.
6. S. Ramanathan, P. C. McIntyre, J. Luning, P. S. Lysaght, Y. Yang, Z. Chen, and S.
Stemmer, J. Electrochem. Soc., 150, F173 ͑2003͒.
7. D. A. G. Bruggeman, Ann. Phys. (Leipzig), 24, 636 ͑1935͒.
8. D. S. McLachlan, J. Phys. C, 19, 1339 ͑1986͒.
9. J. R. Hauser and A. Ahmed, in Conference on Characterization and Metrology for
ULSI Technology, p. 235 ͑1998͒.
30. R. A. B. Devine and A. G. Revesz, J. Appl. Phys., 90, 389 ͑2001͒.
HfO -cubic phase was detected at 850°C. As-determined k-values
2
range from 4.8 (SiO -rich͒ to 15.1 (HfO -rich͒. Both values were
2
2
2
2
determined within approximately 10-15% error. RBS, XPS, and HR-
TEM analysis revealed substantial changes in the homogeneity of
the layers upon RTA, both with and without a polysilicon layer on
top. No dependence of the k-value on the annealing temperature
could be determined, mainly because of the uncertainty in the thick-
ness of the layers after anneal. The leakage currents through an-
nealed layers increase more with temperature than those through
as-deposited layers. This observation suggests that trap-assisted tun-
2
2
2
2
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