Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Article abstract of DOI:10.1063/1.1362331

Structural and electrical properties of gate stack structures containing ZrO₂ dielectrics were investigated. The ZrO₂ films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO₂ films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO₂ layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10^-5 A/cm² at a bias of -1 V from flatband, which is significantly less than that seen with SiO₂ dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (D_it) of ～ 3 × 10¹¹ states/cm eV was determined from comparisons of measured and ideal capacitance curves.

Full text of DOI:10.1063/1.1362331

Electrical and materials properties of ZrO 2 gate dielectrics grown by atomic layer
chemical vapor deposition
Charles M. Perkins, Baylor B. Triplett, Paul C. McIntyre, Krishna C. Saraswat, Suvi Haukka, and Marko
Tuominen
Citation: Applied Physics Letters 78, 2357 (2001); doi: 10.1063/1.1362331
View online: http://dx.doi.org/10.1063/1.1362331
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APPLIED PHYSICS LETTERS
VOLUME 78, NUMBER 16
16 APRIL 2001
Electrical and materials properties of ZrO2 gate dielectrics grown by atomic
layer chemical vapor deposition
Charles M. Perkins, Baylor B. Triplett, and Paul C. McIntyrea)
Department of Materials Science and Engineering, Stanford University, Stanford, California 94305
Krishna C. Saraswat
Department of Electrical Engineering, Stanford University, Stanford, California 94305
Suvi Haukka and Marko Tuominen
ASM Microchemistry, P.O. Box 132, FIN-02631 Espoo, Finland
͑Received 12 September 2000; accepted for publication 12 February 2001͒
Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were
investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition ͑ALCVD͒
after different substrate preparations. The structure, composition, and interfacial characteristics of
these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray
photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal
crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed
between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated
silicon. Gate stacks with a measured equivalent oxide thickness ͑EOT͒ of 1.3 nm showed leakage
values of 10Ϫ5 A/cm2 at a bias of Ϫ1 V from flatband, which is significantly less than that seen
with SiO2 dielectrics of similar EOT. A hysteresis of 8–10 mV was seen for Ϯ2 V sweeps while a
midgap interface state density (Dit) of ϳ3ϫ1011 states/cm eV was determined from comparisons of
measured and ideal capacitance curves. © 2001 American Institute of Physics.
͓DOI: 10.1063/1.1362331͔
Due to increasing levels of direct tunneling current and
reliability problems, SiO2 thinner than approximately 1.5 nm
cannot be used as the gate dielectric for complementary
metal oxide semiconductor technology.1 Many of the con-
ventional high-K candidates studied for capacitor applica-
tions, such as TiO2, Ta2O5, and BST, require a barrier layer
to prevent interdiffusion with the substrate and possible in-
terfacial reactions. With gate applications, however, a single-
layered structure is preferred for process simplicity and mini-
mization of equivalent oxide thickness ͑EOT͒. One of the
most promising material replacements for SiO2 that has been
shown to be thermodynamically stable with respect to solid
state reaction with silicon is ZrO2.1–3 Its stability, along with
its large band gap and dielectric constant of 20–25, make it
an excellent candidate for gate dielectric applications.4,5 In
this letter, we present preliminary results on ZrO2-based gate
stacks deposited by atomic layer chemical vapor deposition
͑ALCVD͒.
deposited directly onto the original chemical silicon oxide of
the as-received wafers. An Al/TiN top electrode was depos-
ited by CVD on all samples and patterned to create 85ϫ85
␮m2 capacitors for electrical testing. No postdeposition an-
neals were performed.
High-resolution transmission electron microscopy
͑TEM͒ micrographs and electron diffraction patterns were
obtained using a Phillips EM430 microscope operating at a
300 kV accelerating voltage, which offers a point-to-point
spatial resolution of 2.0 Å. The cross-sectional TEM micro-
graph in Fig. 1͑a͒ shows the structure of the TiN/ZrO2 /p-Si
MOS capacitor. The micrograph reveals the polycrystalline
nature of the 50 Å film, in addition to the 15 Å interfacial
layer between the ZrO2 and the silicon substrate. From elec-
trical measurements, the EOT of the gate stack is measured
to be 13 Å, which is less than the thickness of the interfacial
layer. This observation supports the proposal that the amor-
phous interfacial layer has a dielectric constant greater than
Ultrathin zirconium oxide films were deposited on 200
mm p-epi/pϩ silicon test wafers using ALCVD at ASM
Microchemistry. The deposition process was performed at
300 °C using alternating surface-saturating reactions of
ZrCl4 and H2O. The first set of samples was patterned before
dielectric deposition to create local oxidation-defined metal-
oxide-semiconductor capacitor ͑MOSCAP͒ structures. Prior
to dielectric deposition, the substrates for these samples were
nitrided by a rapid thermal nitridation in NH3 at a tempera-
ture of 700 °C. The second set of samples was not patterned
before ZrO2 deposition. With this set, the ZrO2 films were
FIG. 1. Cross-sectional TEM micrographs show the morphology of the
TiN/ZrO2 /p-Si gate stack structure on ͑a͒ chemical oxide-terminated silicon
and ͑b͒ HF-last silicon.
a͒
Electronic mail: pcm1@leland.stanford.edu
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0003-6951/2001/78(16)/2357/3/$18.00 2357 © 2001 American Institute of Physics
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2358
Appl. Phys. Lett., Vol. 78, No. 16, 16 April 2001
Perkins et al.
FIG. 3. CV curve of 50 Å ZrO2 film atop a 13 Å nitrided layer reveals EOT
value of 13.8 Å, while JV characteristics show extremely low leakage levels
up to Ϫ3 V.
ther study is needed. Scans of the substrate also showed con-
siderable Si–Zr bonding. We believe this latter signature to
be an artifact of the Ar sputtering process considering the
excellent electrical characteristics of the dielectrics, the lack
of observed zirconium silicide formation during inert ambi-
ent anneals at temperatures up to 1000 °C, and the lack of
silicide signatures in similar samples studied by medium en-
ergy ion spectroscopy ͑MEIS͒.6
FIG. 2. XPS spectra show typical ZrO2 bonding in the bulk dielectric film
and SiO2 bonding in the interfacial layer. Scans are stacked in increasing
angle from 15° on bottom to 90° on top.
that of SiO2. Preliminary electron diffraction studies show
the 30 and 50 Å as-deposited ZrO2 layers to have a cubic
crystal structure. The thickness of the interfacial layer was
found to be largely determined by the pre-deposition Si sur-
face preparation, and not by the ALCVD processing condi-
tions. TEM micrographs of ZrO2 deposited onto HF-last Si
surfaces showed Ͻ5 Å of amorphous interfacial layer ͓Fig.
1͑b͔͒. However, interfacial quality in terms of film roughness
and leakage properties of the MOSCAP structures was poor.
Copel and co-workers have noted similar results and have
suggested that nonuniform hydrogen desorption from the
HF-last surface causes uneven nucleation of ZrO2 during
film deposition.6
X-ray photoelectron spectroscopy ͑XPS͒ profiles were
measured with a Surface Science Instruments S-Probe ͑Al
K␣ x-ray source͒. Angle-resolved scans at 15°, 30°, 60°, and
90° in relation to the film surface are shown in Fig. 2 for a 3
nm ZrO2 film on a 1.4 nm chemical silicon oxide. The 15°
scan shows strong signatures of typical ZrO2 bonding,
namely the shifted Zr 3d oxide doublet at ϳ183 and 185 eV
and the O 1s peak at ϳ531 eV. The scans at steeper angles
show increasing percentages of oxygen bound to Si from
both the O 1s peak at ϳ533 eV and the shifted Si 2p peak at
ϳ103 eV, signifying a silica-based interfacial layer as seen
with TEM. No Si–Zr bonding was noted, suggesting a lack
of silicide formation at the substrate interface and Si–Zr
bonding within the interfacial layer. True silicate bonding
within the interfacial layer was not detectable from any of
the scans ͑i.e., shift to lower binding energy with Si peaks
and shifts to higher energies with Zr and O peaks͒. High
resolution electron energy loss spectroscopy scans also show
little or no Zr incorporation across the interfacial layer.7
Sputter depth profiling XPS was also performed with
these samples. Top surface scans showed similar ZrO2 bond-
ing, however profiles of the interfacial layer showed both
Si–O and Zr–O bonding suggesting a silicate or Zr-doped
silica layer. This mixed bonding arrangement is possibly the
Capacitance–voltage ͑CV͒ and leakage–voltage ͑JV͒
measurements were performed on 85ϫ85 ␮m2 capacitors us-
ing an HP4284A and HP4140B, respectively. The EOT val-
ues for the MOSCAP structures were calculated from the
accumulation capacitance at Ϫ3 V without accounting for
the quantum mechanical effect. Linear extrapolations were
made to leakage as a function of EOT data for sets of ZrO2
and SiO2 samples, both with the same TiN/Al electrode. The
resulting trends show an approximate five orders of magni-
tude improvement in the leakage between capacitors using
SiO2 and ZrO2 at EOT values of 14–15 Å. Similar trends
have been observed with ZrO2 films deposited by reactive
sputtering.8 Figure 3 shows the 100 kHz CV and accumula-
tion JV curves for a 50 Å ZrO2 film deposited atop a 13 Å
nitrided layer. These plots revealed an EOT value of 13.8 Å,
along with a leakage current of approximately 10Ϫ5 A/cm2 at
1 V less than flatband. The same film gave Dit values of
ϳ1ϫ1012 states/cm2 eV. Similar 50 Å ZrO2 films deposited
on a chemical oxide resulted in slightly higher EOT values
due to the smaller permittivity and larger physical thickness
of the interfacial layer. While the leakage values were similar
to those samples deposited on the nitride layer, films depos-
ited on the chemical oxide showed considerable improve-
ments in Dit and hysteresis, as discussed shortly. The Dit
value of ϳ3.1ϫ1011 states/cm2 eV seen with the chemical
oxide samples is expected to improve through use of conven-
tional wet surface preparations and high-quality thermal oxi-
dations. No significant frequency dispersion was seen with
any of the samples.
The dielectric deposition was also scaled back to pro-
duce thinner ZrO2 layers. Figure 4 shows the resulting elec-
trical properties of gate stacks with 20, 35, and 50 Å ZrO2
films. Extrapolating the EOT versus nominal ZrO2 thickness
function to zero suggests a dielectric constant for the inter-
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result of nonuniform sputtering during the etching steps, fur-
facial layer of 6–7, which agrees with other ZrO2 studies
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Appl. Phys. Lett., Vol. 78, No. 16, 16 April 2001
Perkins et al.
2359
FIG. 5. Ten successive Ϯ2 V sweeps show monotonic flatband shift ͑re-
verse sweeps not shown͒.
FIG. 4. Scaled EOT and leakage values for ZrO2 and ZrHfOx films of
varying nominal dielectric thickness.
preparation were caused by elevated fixed charge and trap-
ping resulting from the relatively large nitrogen content near
the dielectric/substrate interface.10 The stress-related ⌬VG
shift is a measure of the drift in the CV characteristics after
successive bias sweeps. As shown in Fig. 5 for a 20 Å ZrO2
film deposited atop a chemical oxide, a shift of 120 mV is
observed after 10 successive Ϯ2 V sweeps ͑reverse sweeps
not included for clarity purposes͒. This phenomenon may
result from several factors such as chemical contamination,
stress-induced defect formation, or mobile-ion transport. The
last possibility seems unlikely since positive-voltage stress-
ing does not shift the CV curves back in the positive-voltage
direction. It is our belief that the ⌬VG shift is a strong func-
tion of the electrode used, and that it indicates a possible
instability of the TiN/Al interface in contact with ZrO2.
concluding the existence of a moderate K-valued interfacial
layer.8 This analysis of the data shown in Fig. 4 assumes that
the interfacial layer is the same for all samples. Subject to
this assumption, the dielectric constant of the ZrO2 layer was
estimated to be between 25 and 35. In a recent study of
reactively sputtered ZrO2, Busch et al. report that only 6 Å
of the 10 Å interfacial layer in their samples can be attributed
to pure SiO2. These authors then mention that some inter-
mixing ͑silicate͒ is likely present in their amorphous interfa-
cial layer.9 At this time, it is unclear how this layer achieves
a moderate dielectric constant. However, the ability to pro-
duce a higher dielectric constant interfacial layer, while
maintaining excellent electrical characteristics, is a key en-
abler of continued scaling of the gate dielectric.
The authors would like to thank E. Garfunkel, M. Kelly,
and P. Pianetta for helpful discussions. This work was sup-
ported in part by the NSF/SRC Engineering Research Center
for Environmentally Benign Semiconductor Manufacturing
and Intel Corporation. One of the authors ͑C.P.͒ acknowl-
edges the support of the Semiconductor Research Corpora-
tion through a graduate fellowship.
Behavior similar to that of ZrO2 was also shown for an
oxide alloy of Hf and Zr, produced by alternating the metal
precursor steps of ZrCl4 and HfCl4. The similarities of the
two metal atoms and metal oxide crystal structures make
possible crystalline ZrO2–HfO2 alloys. These films had
slightly higher EOT values and lower leakage currents than
non-alloyed ALCVD-grown ZrO2 counterparts. Alloying
may allow further optimization of future dielectric films,
possibly in terms of crystallinity and leakage current mini-
mization.
Hysteresis and stress-related ⌬VG shifts were measured
to determine gate stack stability. Hysteresis in the CV curve
is a primary indicator of flatband and threshold voltage sta-
bility due to trapping and/or detrapping of charge in the di-
electric. The hysteresis is voltage dependent, with higher val-
ues resulting for larger voltage range sweeps. When the gate
bias was swept between Ϯ3 V, the hysteresis was approxi-
mately 70–90 mV for the samples with the chemical oxide
layer. For Ϯ2 V sweeps, the hysteresis decreased to 8–10
mV. Samples with the nitride layer produced similar trends
with much larger values. The Ϯ2 V sweeps resulted in hys-
teresis values of approximately 130 mV. We believe these
high hysteresis values for samples with NH3 RTN Si surface
1 Y. Ma, Y. Ono, L. Stecker, D. R. Evans, and S. T. Hsu, Tech. Dig. Int.
Electron Devices Meet. 149 ͑1999͒.
2 D. J. Hubbard and D. G. Schlom, J. Mater. Res. 11, 2757 ͑1996͒.
3 W.-J. Qi, R. Nieh, B. H. Lee, K. Onishi, L. Kang, Y. Jeon, J. C. Lee, V.
Kaushik, B.-Y. Neuyen, L. Phabhu, K. Eisenbeiser, and J. Finder, VLSI
Tech. Dig. 40 ͑2000͒.
4 B. Kralik, E. K. Chang, and S. G. Louie, Phys. Rev. B 57, 7027 ͑1998͒.
5 M. Balog, M. Schieber, M. Michman, and S. Patai, Thin Solid Films 47,
109 ͑1977͒.
6 M. Copel, M. Gribelyuk, and E. P. Gusev, Appl. Phys. Lett. 76, 436
͑2000͒.
7 D. A. Muller and S. Ramanathan ͑private communication͒.
8 W.-J. Qi, R. Nieh, B. H. Lee, L. Kang, Y. Jeon, K. Onishi, T. Ngai, S.
Banerjee, and J. C. Lee, Tech. Dig. Int. Electron Devices Meet. 145
͑1999͒.
9 B. W. Busch, W. H. Schulte, E. Garfunkel, T. Gustafsson, W. Qu, R.
Nieh, and J. Lee ͑in press͒.
10 G. Lucovsky and J. C. Phillips, J. Non-Cryst. Solids 227–230, 1221
͑1998͒.
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