Minimizing the Effects of Hardware Marginality on Charging Damage during Plasma-Enhanced Chemical Vapor Dielectric Deposition

Article abstract of DOI:10.1149/1.1414289

In this paper, Kelvin-probe measurements, antenna transistors, and electrically programmable read-only memory cells are used to minimize the influence of hardware marginality on charging damage during plasma-enhanced chemical vapor deposition of dielectric films. It is shown that charging during tetraethosiloxane (TEOS) deposition can be reduced by increasing the deposition pressure and optimizing the plasma ramp-down after deposition. It is also demonstrated that differences in the charging performance between tools from different vendors during the deposition of silicon-rich oxides can be smoothed out if a double radio frequency process replaces the traditional single radio frequency deposition.

Full text of DOI:10.1149/1.1414289

Journal of The Electrochemical Society, 148 ͑12͒ F207-F211 ͑2001͒
F207
0
013-4651/2001/148͑12͒/F207/5/$7.00 © The Electrochemical Society, Inc.
Minimizing the Effects of Hardware Marginality on Charging
Damage during Plasma-Enhanced Chemical Vapor
Dielectric Deposition
Antonio Cacciatoz
Philips Semiconductors, MOS 4 YOU, 6534 AE Nijmegen, The Netherlands
In this paper, Kelvin-probe measurements, antenna transistors, and electrically programmable read-only memory cells are used to
minimize the influence of hardware marginality on charging damage during plasma-enhanced chemical vapor deposition of
dielectric films. It is shown that charging during tetraethosiloxane ͑TEOS͒ deposition can be reduced by increasing the deposition
pressure and optimizing the plasma ramp-down after deposition. It is also demonstrated that differences in the charging perfor-
mance between tools from different vendors during the deposition of silicon-rich oxides can be smoothed out if a double radio
frequency process replaces the traditional single radio frequency deposition.
©
2001 The Electrochemical Society. ͓DOI: 10.1149/1.1414289͔ All rights reserved.
Manuscript received March 15, 2001. Available electronically November 2, 2001.
Plasma processes are widely used in microelectronic manufactur-
ing for anisotropic etching, surface cleaning, and low-temperature
plasma-enhanced chemical vapor deposition ͑PECVD͒ of thin
gas. After deposition, a ramp-down step was performed using a
He ϩ O plasma ͑5 s at 200 W, 8 Torr, 1200 sccm He, 1000 sccm
2
O ͒. Variants to the standard process were obtained varying the
2
1
films. During plasma processing, wafers are subjected to the direct
deposition pressure in the range from 5 to 15 Torr, the oxygen flow
in the range 500 to 2000 sccm, the deposition temperature, and the
TEOS flow. For all the variants, the thickness of the TEOS layer was
bombardment of ions, electrons, and photons. In uniform plasma the
ion and electron conduction locally balance each other over the rf
2
cycle. In this case, the surface potential stays close to that of the
500 nm, i.e., the same of the standard process.
substrate. In nonuniform plasma, however, the situation differs sig-
nificantly. Ion and electron currents do not balance locally during the
rf cycle, although there is a net balance over the electrode as a
whole. In this case, charges ͑positive or negative depending on spe-
cific ratio between positive and negative currents͒ start to accumu-
late on the wafer regions covered by insulating films. The charge
buildup continues until the electric field across gate oxides reaches
values high enough to allow Fowler-Nordheim ͑FN͒ tunneling of
charges. This causes what is usually called plasma charging damage,
i.e., trap formation, wear out, and premature breakdown of thin gate
oxides. Moreover, it increases the probability of charge trapping in
the oxide. As a consequence, shifts of the threshold voltage, leakage,
degraded circuit speed, and deterioration of transistor matching may
occur. As device dimensions and gate oxide thicknesses are scaled
SILOX deposition.—300 nm PECVD silicon-rich oxide films were
deposited on 200 mm wafers. Prior to SILOX deposition, EPROM
cells were fabricated on the same wafers using a 0.35 ␮m comple-
mentary metal oxide semiconductor ͑CMOS͒ technology. Deposi-
tion was carried out at a temperature of 400°C, a pressure of 2.5
Torr, an rf power of 250 W and using a SiH ϩ N O gas chemistry.
4
2
The deposition time was ca. 15 s. Unlike for TEOS films, after
deposition the plasma was switched off without a He ϩ O plasma
2
ramp-down. SILOX layers were deposited using either batch or
single-wafer PECVD reactors. In the case of the batch reactor, the
chamber allowed the deposition of six wafers at the same time. The
SiH flow was 130 and 300 sccm for the single-wafer and batch
4
3
4
reactor, respectively. The N2O flow was 800 sccm ͑single-wafer re-
actor͒ or 9500 sccm ͑batch reactor͒. In some cases, in addition to the
down, charging becomes an increasing reliability or yield concern.
To limit charging damage, tight control of plasma uniformity and
knowledge of the interaction among plasma, hardware, and process
1
3.5 MHz rf power used to decompose the SiH ϩ N O gas mixture
4 2
5
and ignite the plasma, a low-frequency ͑10 kHz͒ rf power was ap-
plied to the wafer susceptor to enhance the ion bombardment on the
as-deposited film. Double rf recipes are used in microelectronic
manufacturing because the ion bombardment improves the quality
settings are mandatory. In this paper, these issues are addressed by
6
using fast-feedback noncontact Kelvin-probe measurements, an-
tenna transistors, and electrically programmable read-only memory
cells ͑EPROM͒7 to measure charging during plasma-enhanced
1
0
͑stability and density͒ of the insulating layers.
chemical vapor deposition of two materials widely used in micro-
electronic manufacturing for interlayer and intermetal insulation, tet-
Charging measurements.—Kelvin probe.—During PECVD
8
9
raethosiloxane ͑or TEOS͒ and the silicon-rich oxide ͑or SILOX͒.
deposition of insulating layers, charges may accumulate in the bulk
as well as on the surface of the wafer if the plasma in unstable.
These charges change the surface potential of the wafer. Therefore, a
measurement of the wafer surface potential can be used to detect
charging. In this work, the surface potential after PECVD TEOS
deposition was measured using the Kelvin probe technique. The
probe consists of a noncontact sensor that detects the ac signal in-
duced by an oscillating shutter positioned between the electrode and
the wafer surface. Measurements were carried out applying different
dc biases across the sensing electrode and a grounded electrode until
the ac voltage is reduced to zero. The bias at which the ac voltage is
zero is equivalent to the wafer surface potential. A more detailed
description of probe functioning can be found in Ref. 11. Kelvin
probe measurements were performed using the plasma damage
monitor system manufactured by Semiconductor Diagnostics, Inc.
The distribution of the surface potential on the wafer was evaluated
by measuring 6000 points per wafer.
In particular, the relation between plasma ramp-down, reactor archi-
tecture ͑single-wafer or batch͒, and charging is investigated. Pos-
sible ways to optimize the deposition process in order to minimize
the influence of process-hardware marginality on charging are also
discussed.
Experimental
Dielectric deposition.—TEOS deposition.—SiO layers ͑500 nm
2
thick͒ were deposited on 200 mm wafers using plasma-enhanced
chemical vapor deposition ͑PECVD͒ by decomposition of tetra-
8
ethosiloxane, Si͑OC H ͒ , better known as TEOS, Si͑OC H ͒
2
5 4
2
5 4
ϩ O → SiO ϩ CO ϩ OH. The deposition was carried out for 45
2
2
s at 400°C using an rf power of 675 W and a deposition pressure of
8
1
Torr. During deposition, the TEOS and O flows were 1200 and
000 sccm, respectively. Helium ͑1200 sccm͒ was used as a carrying
2
Threshold voltage shift.—Surface potential measurements have been
compared with threshold voltage measurements of n- and p-channel
z
E-mail: antonio.cacciato@philips.com
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Journal of The Electrochemical Society, 148 ͑12͒ F207-F211 ͑2001͒
Figure 2. Average surface potential after 500 nm PECVD TEOS deposition
carried out on each of the four chambers ͑A, B, C, D͒ of the two single-wafer
PECVD reactors X and Y. Nine points were measured on each wafer.
EPROM cells after PECVD deposition then allows the estimation of
the charging-induced voltage the cells have been exposed to. In this
work the threshold voltage of the cell has been defined as the volt-
age that is necessary to apply to the control gate to measure at the
drain a current of 1 ␮A when the potential difference between
source and drain is Vds ϭ 0.1 V.
Figure 1. XTEM of the EPROM cell used in this work.
An important parameter for the capability of the EPROM cells to
detect charging is the fraction of the voltage applied to the control
gate that is coupled to the floating gate ͑the so-called coupling factor
␣͒. The higher the coupling factor, the higher the voltage across the
oxide in the case of charging and, as a consequence, the more elec-
trons can tunnel into the FG. The coupling factor for the cells con-
sidered in this work was 0.79 Ϯ 0.4. This value is higher than that
of conventional stacked-gate EPROM cells because the CG of the
transistors connected to large metal or poly-Si antenna plates. The
antenna improves charge collection during plasma exposure, thus
increasing the FN current density in the gate oxide.12 This amplifies
the effect of charging on the transistor properties. In general, the
larger the ratio is between the area of the antenna and the area of the
MOS gate ͑the so-called antenna ratio͒, the higher the FN current
and, consequently, the more affected the transistor is by charging.
The antenna transistors used in this work were fabricated in a
standard three-metal 0.5 ␮m CMOS process. The antenna ratio for
the transistors with antenna at poly-1, metal 1, or metal 2 was 550.
The antenna ratio for the transistors with antenna at metal 3 was
1
3
cell in Fig. 1 completely overlaps the FG.
To study charging during PECVD deposition, the threshold volt-
age of the EPROM cells has been measured before and after erasure
of the cells. Erasure has been achieved by illuminating the cells with
UV light. During UV illumination, the energy necessary for the
stored electrons to surmount the energy barriers surrounding the
1
4
1840. The severity of charging was estimated by calculating the total
floating gate is provided by the UV photons.
fraction of antenna transistors whose threshold voltage shifted ͑with
respect to the threshold voltage of a reference transistor not con-
nected to any antenna͒ more than a fixed value.
In addition to the threshold voltage of the standard cells, the Vt
of a reference cell placed at a distance of 3 ␮m from the standard
EPROM cell was also measured. In the reference cell the floating
and control gates are shorted. This allowed the separation of thresh-
old voltage shifts due to charges trapped in the floating gate from
shifts due to wafer-to-wafer variations of the cell morphology ͑like
oxide thickness or floating gate length variations͒.
EPROM cells.—In addition to Kelvin probe and antenna transistors,
charging was also studied by means of electrically programmable
read-only memory ͑EPROM͒ cells processed in a 0.35 ␮m CMOS
technology. The cells were n-channel devices with gate length,
width, and oxide thickness of 0.35 ␮m, 0.5 ␮m, and 8 nm, respec-
tively. The cross-sectional transmission electron microscopy
Results and Discussion
͑
XTEM͒ of a typical cell is given in Fig. 1. The cell is formed by an
TEOS deposition.—TEOS layers, 500 nm thick, were deposited
on unpatterned Si wafers using the standard process. Deposition was
performed on each of the four chambers ͑A, B, C, and D͒ of two
different single-wafer PECVD reactors ͑X and Y͒. After deposition,
Kelvin-probe measurements of the wafer surface potential were car-
ried out. Results are shown in Fig. 2. The average surface potential,
VSpave , is Ϫ2 V Ͻ VSPave Ͻ Ϫ1 V for all the wafers of reactor X
and for those processed in the chambers A, B, or C of the reactor Y.
This value is close to the detection limit of the Kelvin-probe system
͑Ϯ1 V͒, indicating negligible charging during deposition. The situ-
ation is different for the wafer processed in chamber D of the reactor
Y. In this case the absolute value of the surface potential is much
higher ͑7 V͒, suggesting charging during deposition.
insulated poly-Si layer ͑the floating gate, FG͒, completely over-
lapped by a second poly-Si layer ͑the control gate, CG͒. The FG is
electrically insulated from the CG and the Si substrate by the 8 nm
gate oxide, by the sidewall oxide, and by the oxide-nitride-oxide
͑
ONO͒ stack ͑oxide equivalent thickness ca. 20 nm͒.
The principle of operation of the EPROM cell is similar to that of
an ordinary MOS transistor. For a given potential difference be-
tween source and drain, the current flows only if the voltage applied
to the CG is higher than the threshold voltage V . The difference
with respect to an ordinary transistor is that the threshold voltage of
an EPROM cell is controlled by the charges trapped in the FG.
This property makes the EPROM cells suitable for detect charging.
In fact, if, because of charging, a voltage is applied to the control
gate during, for example, deposition of SILOX or TEOS, the voltage
across the gate oxide increases and electrons start tunneling from the
t
7
The influence on the anomalous behavior of chamber D of the
plasma ramp-down step is investigated in Fig. 3. Four different
ramp-down processes were carried out after the standard 500 nm
TEOS deposition: ͑1͒ XX: no plasma and no He or O2 flow; ͑2͒
silicon substrate into the floating gate, thus increasing the V of the
t
EPROM cell. A simple measure of the threshold voltage of the
NP: He and O flow but no plasma; ͑3͒ He: only He plasma ͑1200
2
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Journal of The Electrochemical Society, 148 ͑12͒ F207-F211 ͑2001͒
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Figure 5. Five-lot average of the fraction of antenna transistors with high
threshold voltage shift due to poly, metal 1, metal 2, metal 3 charging.
Figure 3. Average surface potential after 500 nm TEOS deposition per-
formed in chambers C and D of the PECVD system Y for different ramp-
down processes. Nine points were measured on each wafer.
calculated. As illustrated in the figure, VSPave is 40 V at 5 Torr, it
reduces to 24 V at the pressure of 8 Torr ͑standard deposition pres-
sure͒, and it decreases almost to zero if the pressure is further in-
creased to 12 V. A similar trend is observed for ⌬VSP . No effect of
the oxygen flow are observed instead. These results indicate that an
increased deposition pressure may reduce the effect of defective
hardware on charging.
The effect of disabling the defective chamber and of the intro-
duction of an optimized recipe with a higher deposition pressure on
the threshold voltage of the antenna transistors is shown in Fig. 5. In
this figure the total fraction of antenna transistors with threshold
voltage higher than the upper specification limit a is displayed as a
function of the process time. At the beginning, a large spread in the
failing fraction was observed. This spread was reduced, but not
completely suppressed, after the defective chamber D was put down
for production. Finally, after the introduction of the optimized
recipe, the failing fraction reduced practically to zero. Results in
Fig. 5 confirm those obtained by Kelvin-probe measurements and
indicate that when, as in the case considered here, instability occurs
during the last moments of the plasma process, the Kelvin-probe
technique can be used as a fast feedback technique to monitor charg-
ing.
sccm͒ during ramp-down; ͑4͒ He ϩ O : standard ramp-down in a
2
He and O plasma ͑1200 sccm He, 1000 sccm O ͒. This is the same
2
2
ramp-down used in the case of data in Fig. 2.
For each variant, one wafer was processed in chamber C and one
wafer in chamber D of the Y system. The average surface potential
for each of the eight wafers is plotted in Fig. 3. Negligible differ-
ences between C and D are observed if no plasma is ignited during
ramp-down ͑variants 1 and 2͒. The same is obtained if only He
plasma is used ͑variant 3͒. However, if He ϩ O plasma is used
2
during ramp-down ͑variant 4͒, the surface potential measured for
chamber D is ca. Ϫ18 V whereas that measured for chamber C is
only ca. Ϫ2 V.
Results in Fig. 3 indicate that the anomalous behavior of cham-
ber D is triggered during plasma ramp-down after deposition. They
also illustrate the relevance of the hardware-process interaction for
charging. In fact, they indicate that the risk of charging in the pres-
ence of hardware marginality ͑chamber D is behaving differently
from chamber C͒ is enhanced by a wrong process choice ͑ramp-
down in a He ϩ O plasma͒.
2
The issue of process optimization to reduce charging in the pres-
ence of hardware marginality is discussed in Fig. 4. TEOS layers
were deposited at pressures ranging from 4 to 15 Torr and at three
different oxygen flows using the defective chamber of system Y
SILOX deposition.—SILOX films, 300 nm thick, were deposited
on 200 mm wafers as part of the dielectric stack that insulates the
control gate of EPROM cells from the first metal layer. The depo-
sition was carried out using a single-frequency recipe and two dif-
ferent reactors: a single-wafer reactor and a batch reactor. The
threshold voltage of the EPROM cells was measured immediately
after the deposition and patterning of the first metal layer.
͑
chamber D͒. After deposition, the wafer surface potential was mea-
sured on nine points per wafer and VSPave and ⌬VSP have been
Figure 6 shows the cumulative distributions of the threshold volt-
age before and after UV erasure. Before UV erasure, the distribution
is shifted to higher values when the single-wafer tool is used. In fact,
the 50% value of the distribution is 1.6 and 1.3 V for the single-
wafer and the batch reactor, respectively. The spread Vtmax Ϫ Vtmin
of the threshold voltage in the wafer is also higher for the single
wafer than for the batch reactor, 0.6 and 0.3 V, respectively. The
difference between the two systems disappears after UV erasure,
demonstrating that the cause was a difference in the amount of
charges trapped in the floating gate. This difference can be quanti-
fied using the relation between the charge trapped in the FG, ⌬Q
,
FG
7
and the shift, ⌬V , of the threshold voltage after UV erasure
t
⌬
QFG
⌬
V ϭ Ϫ
t
͓1͔
CG
Figure 4. Average surface potential (VSpave) and in-wafer spread (⌬VSP
ϭ VSpmax Ϫ VSpmin) vs. the deposition pressure for different oxygen flows.
The TEOS layers ͑500 nm thick͒ were deposited using chamber D of system
Y. Nine points were measured on each wafer.
where C , the capacitance between the control and floating gates, is
equal to
G
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Journal of The Electrochemical Society, 148 ͑12͒ F207-F211 ͑2001͒
Figure 6. Cumulative distributions of the threshold voltage V of EPROM
cells processed either in the single-wafer or in the batch reactors. Distribu-
t
Figure 8. Cumulative distributions of the threshold voltage V of EPROM
t
cells processed either in the single-wafer or in the batch reactors. The SILOX
deposition was carried out either using single-frequency ͑SF͒ or double-
frequency ͑DF͒ recipes.
tions before and after UV erasure are compared. The V measurements were
t
performed after metal 1 deposition.
wafer-to-wafer variations of the cell morphology ͑like oxide thick-
ness or floating gate length variations͒ but to charge trapped in the
FG.
KL␧0␧ox
͑2Kϩ2L͒H␧0␧ox
CG
ϭ
ϩ
͓2͔
tONOeff
tSWeff
The results in Fig. 6 and 7 illustrate that charging is higher in the
single-wafer reactor than in the batch reactor. This is probably due
to the fact the rf power is applied to a single wafer in the first case
whereas it is divided among six wafers in the second. Data in Fig. 8
illustrate that the use of a double-frequency recipe can reduce the
influence the reactor architecture has on charging. In the figure, the
cumulative distributions of the threshold voltage for the two reactors
͑single wafer and batch͒ and the two deposition recipes ͑double and
single frequency͒ are compared. In the case of the single-frequency
deposition the difference between the two reactors is similar to that
already seen in Fig. 6. However, the difference disappears if the
double-frequency recipe is used. In this case, a low-frequency ͑10
kHz͒ rf power is applied to the wafer chuck in addition to the stan-
dard 13.5 MHz rf power used to ignite the plasma. The addition of
the extra rf power allows the optimization of the ion plasma ͑ions
are too heavy to react efficiently to the 13.5 MHz frequency͒ inde-
pendently from that of the electron plasma. This results in better
control of the plasma uniformity and, as consequence, in a lower
charging level even in the case of the single-wafer reactor.
In Eq. 2, tONOeff and tSWeff are the effective thicknesses of the ONO
Ϫ12
layer and sidewall dielectric, ␧ ϭ 8.854 ϫ 10
F/m is the per-
0
mittivity of the free space and ␧ox ϭ 3.9 is the oxide dielectric
constant, K, L, and H indicate the width, the length, and the height
of the floating gate, respectively. For the cells used in this study it is
tONOeff Ϸ 20 nm tSWeff ϭ 33 nm, K ϭ 1.4 ␮m, L ϭ 0.35 ␮m,
Ϫ15
H ϭ 0.2 ␮m. Equation 2 then yields CG Ϸ 1.58 ϫ 10
F. Fig-
ure 6 shows that the shift of the threshold voltage after UV erasure
is ⌬V ϭ 0.5 V and ⌬V ϭ 0.2 V for the single wafer and the
t
t
batch reactor, respectively. From Eq. 1 and 2 it follows then ⌬Q
FG
Ϫ15
Ϫ15
ϭ 0.82 ϫ 10
C and ⌬QFG ϭ 0.35 ϫ 10
C for the single wa-
fer and the batch reactor, respectively.
The threshold voltage distributions of the reference transistors
͑
i.e., EPROM cells in which FG and CG are shorted͒ for the same
variants as in Fig. 6 are shown in Fig. 7. The threshold voltage for
the reference transistors is smaller than for the EPROM cells. This is
expected. In fact, the potential drop across the ONO layer which
lowers the potential of the FG in the EPROM cell is absent in the
reference transistor, where FG and CG are shorted. More interesting,
Sensitivity of the EPROM cell to charging.—In the presence of
charging the floating gate potential rises to a value VFG ϭ ␣VCG ͑␣
and VCG being the coupling factor of the cell and the control gate
potential, respectively͒. As a consequence, the following FN current
the V distributions are similar for all variants, confirming that the
t
differences between the two reactors seen in Fig. 6 are not due to
1
5
flows from the substrate into the FG
B
2
J ϭ AE exp
ͩ
Ϫ
ͪ
͓3͔
ox
Eox
where E ϭ ␣VCG /dox is the electrical field in the oxide of thick-
ness dox . In Eq. 3 A, B are constants related to the tunneling barrier
ox
a
height ⌽ and to the effective mass of the tunneling electron in the
1
6
oxide mox by the equations
4
3
ͱ
2mox
qប
B ϭ
⌽3/2
͓4͔
͓5͔
q3
A ϭ
2
1
6␲ ប⌽
a
In general it should be written Eox ϭ (␣VCG Ϫ VT)/dox with VT being the voltage
Figure 7. Cumulative distributions of the threshold voltage of reference
transistor ͑i.e., an EPROM cell in which control and floating gates are in
short͒. The same variants as in Fig. 6 are compared.
necessary to create the inversion layer in the EPROM channel. However, at the tem-
perature used for plasma deposition ͑400°C͒ the Si substrate becomes intrinsic ͑see Ref.
18͒ and no inversion layer has to be created to inject electrons in the FG.
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Journal of The Electrochemical Society, 148 ͑12͒ F207-F211 ͑2001͒
F211
where ͑ប ϭ 6.63 ϫ 10Ϫ34/2␲ kg m s and q ϭ 1.6 ϫ 10
2
Ϫ1
Ϫ19
C͒.
recipe with an increased deposition pressure, the shift of the thresh-
old voltage of antenna transistors was drastically reduced.
Results 1 and 2 demonstrate that the effect on charging of defec-
tive hardware or nonoptimal system architecture can be reduced by
more careful process choices. Result 3 indicates that the Kelvin-
probe technique can be successfully used as a fast feedback tech-
nique for charge monitoring and process optimization when, as in
the case of TEOS deposition, charging occurs at the end of the
plasma process.
ϩ
For the EPROM cell of Fig. 1, the gate material is n -type
poly-Si and the gate oxide is 8 nm thick. In this case, ⌽ Ϸ 3.25
eV, mox ϭ 0.32m ͑where m ϭ 9.11 ϫ 10
rest mass͒, and A and B equal 4.83 ϫ 10
1
6
Ϫ31
kg is the electron
m /V and 7.54
e
e
17
Ϫ7
2
2
ϫ 109 V/m, respectively.
If VFG ͑and therefore J͒ is assumed constant during SILOX depo-
sition, then the charge trapped in the FG is equal to ⌬QFG ϭ J
ϫ t ͑t is the deposition time͒. As calculated in the previous section,
⌬
QFG ϭ 0.82 ϫ 10Ϫ15 C and ⌬QFG ϭ 0.35 ϫ 10Ϫ15 C for the
single wafer and the batch reactor, respectively. For a deposition
Acknowledgments
time of ca. 15 s the previous equation then yields J ϭ 5.5
Ϫ17
Ϫ17
ϫ 10
A for the single-wafer reactor and 2.3 ϫ 10
A for the
Part of this work was financially supported by the MEDEA
Project T501. K. Druijf, P. Schumbera, J. R. M. Luchies, and A.
Scarpa ͑Philips Semiconductors, MOS4YOU, Nijmegen͒ are ac-
knowledged for their help during the measurements and their useful
comments and suggestions.
batch reactor. Substituting these values in Eq. 3 and solving it with
respect to VCG , it is found that the effective voltage applied to the
control gate during deposition is VCG Ϸ 1.27 V and VCG
b
Ϸ 1.24 V for the two reactors. This result illustrates the capability
of the EPROM cell to resolve differences as low as 30 mV in the
average charging performance of different deposition systems.
Philips Semiconductors assisted in meeting the publication costs of this
article.
Conclusions
References
In this work, PECVD TEOS and SILOX deposition were studied
using the Kelvin probe technique, EPROM cells, and antenna tran-
sistors. It was found that
1
. S. Wolf and R. N. Tauber, in Silicon Processing for the VLSI Era, p. 184, Lattice
Press, Sunset Beach, CA ͑2001͒.
2. C. T. Gabriel and J. P. McVittie, Solid State Technol., 1992, 81 ͑June͒.
3. S. R. Nariani and C. T. Gabriel, IEEE Electron Device Lett., 16, 242 ͑1994͒.
4. J. R. M. Luchies, P. L. L. Simon, F. G. Kuper, and W. Maly in Proceedings
P2ID-98 Conference, p. 7, Hawaii ͑1998͒.
1. Charging due to a defective deposition chamber is triggered if
oxygen is added to the plasma gases during plasma ramp-down after
TEOS deposition. No effect of the defective chamber on charging is
detected if only helium is used instead.
5. C. R. Viswanathan, Microelectron. Eng., 49, 65 ͑1999͒.
6
7
. A. M. Hoff, T. C. Esry, and K. Nakua, Solid State Technol., 39„7…, 139 ͑1996͒.
. P. Olivo and E. Zanoni, in Flash Memories, P. Cappelletti, C. Golla, P. Olivo, and
E. Zanoni, Editors, Kluwer Academic Publishers, Dordrecht ͑1999͒.
2. Single-wafer reactors are found to cause more charging than
batch reactors during SILOX deposition. However, this sensitivity to
the reactor chamber architecture is suppressed if deposition is car-
ried out with an additional low-frequency rf power applied to the
wafer susceptor.
8
. R. M. Levin and C. Adams, J. Electrochem. Soc., 126, 1042 ͑1979͒.
9. C.-F. Lin, W.-T. Tseng, and M. S. Feng, J. Appl. Phys., 87, 2808 ͑2000͒.
0. C.-F. Lin, W.-T. Tseng, and M. S. Feng, Jpn. J. Appl. Phys., Part 1, 37, 6364
1
͑
1998͒.
1. Y. Tada and Y. Tomizawa, Jpn. J. Appl. Phys., Part 1, 34, 643 ͑1995͒.
2. C. T. Gabriel, J. Vac. Sci. Technol. A, 17, 1494 ͑1999͒.
13. A. Walker, U.S. Pat. 5,395,778 ͑1995͒.
4. R. D. Katznelson and D. F.-B. Kowsky, IEEE Trans. Electron Devices, ED-27,
744 ͑1980͒.
5. M. Lenzlingen and E. H. Snow, J. Appl. Phys., 40, 278 ͑1969͒.
16. C. M. Osburn and E. J. Weitzman, J. Electrochem. Soc., 119, 603 ͑1972͒.
17. M. Depas, B. Vermeire, P. W. Mertens, R. L. van Meirhaeghe, and M. M. Heyins,
Solid-State Electron., 38, 1465 ͑1995͒.
1
1
3. Deposition pressure affects charging during TEOS deposition.
Kelvin-probe measurements suggested that an increase of the depo-
sition pressure could optimize the recipe. After the introduction of a
1
1
1
b
These values should be considered as the lower limit for the maximum voltage
seen by the cell during processing. In fact, in general, the voltage is constant neither in
its absolute value nor in its polarity during the deposition. As a consequence, the charge
⌬
QFG trapped in the floating gate at the end of the plasma deposition is the result of a
18. R. F. Pierret, in Semiconductor Fundamentals, Modular Series on Solid State De-
vices, R. F. Pierret and G. W. Neudeck, Editors, Addison-Wesley Publishing, Read-
ing, MA ͑1989͒.
balance between the negative and positive charges injected in the floating gate during
the different phases of the plasma process.
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