Metal nanocrystals synthesized with a micellar template based on a diblock copolymer for three-dimensional nonvolatile memory

Article abstract of DOI:10.1063/1.2969051

Metal nanocrystals synthesized with a micellar template were applied for three-dimensional vertical floating gate memory devices. Using a highly ordered micellar template formed with a diblock copolymer, we produced cobalt (Co) nanocrystals with a uniform size and spatial distribution on a planar surface and a sidewall surface. The hydrogen annealing effects were investigated in terms of memory performance. The fabricated vertical floating gate memory with Co nanocrystals annealed with hydrogen showed a memory window with a voltage greater than 1 V and a retention time characteristic that preserves more than 60% of the initial charge after ten years.

Full text of DOI:10.1063/1.2969051

Metal nanocrystals synthesized with a
micellar template based on a diblock
copolymer for three-dimensional
nonvolatile memory
Cite as: Appl. Phys. Lett. 93, 052106 (2008); https://doi.org/10.1063/1.2969051
Submitted: 15 April 2008 . Accepted: 14 July 2008 . Published Online: 08 August 2008
Chung-Jin Kim, Seong-Wan Ryu, Yang-Kyu Choi, Jae-Joon Chang, Su Hak Bae, and Byeong-Hyeok
Sohn
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Appl. Phys. Lett. 93, 052106 (2008); https://doi.org/10.1063/1.2969051
93, 052106
© 2008 American Institute of Physics.

APPLIED PHYSICS LETTERS 93, 052106 ͑2008͒
Metal nanocrystals synthesized with a micellar template based on a diblock
copolymer for three-dimensional nonvolatile memory
Chung-Jin Kim,1 Seong-Wan Ryu,1 Yang-Kyu Choi,1,a͒ Jae-Joon Chang,2 Su Hak Bae,2
and Byeong-Hyeok Sohn2
1School of Electrical Engineering and Computer Science, Division of Electrical Engineering,
Korea Advanced Institute of Science and Technology, Daejeon 305-701, Republic of Korea
2Department of Chemistry and NANO Systems Institute, Seoul National University, Seoul 151-747,
Republic of Korea
͑Received 15 April 2008; accepted 14 July 2008; published online 8 August 2008͒
Metal nanocrystals synthesized with a micellar template were applied for three-dimensional vertical
floating gate memory devices. Using a highly ordered micellar template formed with a diblock
copolymer, we produced cobalt ͑Co͒ nanocrystals with a uniform size and spatial distribution on a
planar surface and a sidewall surface. The hydrogen annealing effects were investigated in terms of
memory performance. The fabricated vertical floating gate memory with Co nanocrystals annealed
with hydrogen showed a memory window with a voltage greater than 1 V and a retention time
characteristic that preserves more than 60% of the initial charge after ten years. © 2008 American
Institute of Physics. ͓DOI: 10.1063/1.2969051͔
On behalf of the rapid growing nonvolatile memory
͑NVM͒ technology, flash memory device is in great demand
on account of their high density memory. This demand has
been accelerated by the advent of mobile device and the
increase of multimedia data amount. As the scaling down of
device becomes accelerated, some critical issues are un-
avoidable, such as limitations in the downscaling of a tun-
neling oxide thickness and cell-to-cell crosstalk. To break
through the innate limitations of conventional flash memory
with a continuous polycrystalline silicon layer, profound re-
search on nanocrystal ͑NC͒-embedded memory has been
proposed,1and the latest research is concentrated on metal
NC. Metal NC has many advantages over Si NCs, which
were mainly studied in the early stage of NC-embedded
memory research.2 Recently, polymeric template-assisted
methods have been proposed for the formation of metal NCs.
Based on self-assembled porous template using phase sepa-
ration, these methods aim to circumvent the variation prob-
lem with the cell-to-cell threshold voltage ͑VT͒. The variation
problem is due to the nonuniform size and distribution of
NCs at the time of the scaling down.3–5
In spite of such advanced methods of NC formation, the
fundamental physical limitations on effective gate length,
tunnel oxide thickness, and drive current are not eliminated
in a conventional memory cell that uses a planar structure.6,7
One way of overcoming these limitations is to use three-
dimensional ͑3D͒ devices that can suppress short-channel ef-
fects through structural change.7–10 Because conventional
methods of NC formation are unsuitable for 3D devices with
a double gate and triple gate structure, few studies have ex-
amined silicon NCs formation, and there appears to be no
research on the controlled formation of single-layered metal
NCs with a vertical sidewall structure.11,12 Finding a method
that can make uniformly distributed metal NCs on a sidewall
surface and on the top surface is crucial for achieving 3D
multiple-gate NVM for ultimate scaling.
Thus, the fabrication and characterization of 3D vertical
floating gate memory with metal NCs are presented in this
work for ultimately scaled NVM. The aforementioned poly-
meric template assisted method is suitable only for a planar
structure. However, in our dipping method, we use a micellar
structure based on a diblock copolymer as a sacrificial tem-
plate. Through adjustment of the dip coating condition, re-
versed micelles based on a block copolymer can be coated as
a Langmuir–Blodgett monolayer film on any preferred re-
gion of the substrate, and these reversed micelles are rear-
ranged in a hexagonal-ordered form due to the equal size of
each micelle. Moreover, we can easily and precisely manipu-
late the NC diameter and NC-to-NC space by modulating the
molecular weight in a core block and in the shell block that
surrounds the core block.13 Note also that we investigated
how hydrogen annealing for metal reduction affects memory
performance.
Figure 1 shows a schematic diagram of the fabrication of
a single-layered array of Co NCs on a 3D vertical floating
gate memory cell with utilization of block copolymer mi-
celles. Polystyrene-block-poly͑4-vinyl pyridine͒ ͑PS-PVP͒
copolymers were purchased from Polymer Source, Inc. The
average molecular weight was 32 900 g/mol for the PS and
8000 g/mol for the PVP. The polydispersity index was 1.08.
The PS-PVP copolymers were dissolved in toluene at 75 °C
to yield a 0.5 wt % micellar solution, which was then cooled
down to room temperature ͓Fig. 1͑a͔͒. In the toluene, which
is a strongly selective solvent for the PS block, the PS-b-PVP
copolymers spontaneously associated into spherical reverse
micelles of a nonpolar PS corona and a polar PVP core. To
synthesize the Co NCs, we selectively loaded the precursor
cobalt chloride into the PVP core ͓where the molar ratio of
CoCl2/vinyl pyridine was 0.5, Fig. 1͑b͔͒ because cobalt chlo-
ride, a transition metal salt, can be coordinated to the lone-
pair electron of the pyridine unit in the PVP block.14,15 From
the PS-PVP micellar solution with CoCl2, a single layer of
the micelles in hexagonal order was coated on the vertical
floating gate memory cell by dip coating at a rate of 20
mm/min. As shown in the schematic diagram of Fig. 1͑c͒, a
a͒
Author to whom correspondence should be addressed. Electronic mail:
ykchoi@ee.kaist.ac.kr.
0003-6951/2008/93͑5͒/052106/3/$23.00
93, 052106-1
© 2008 American Institute of Physics

052106-2
Kim et al.
Appl. Phys. Lett. 93, 052106 ͑2008͒
FIG. 2. ͑Color online͒ A SEM image of Co NCs on ͑a͒ the top surface and
͑b͒ the sidewall surface. The inset shows a 3D schematic diagram of the 3D
vertical floating gate memory with NCs on the sidewall and the top.
an exposed whole Si surface.17 Finally, the forming gas was
performed for 1 h at 400 °C.
FIG. 1. ͑Color online͒ A schematic illustration of NCs fabrication on the
sidewall and top of the vertical floating gate memory. ͑a͒ PS-PVP micellar
solution. ͑b͒ PS-PVP micellar solution with CoCl2 in the PVP core. ͑c͒
Monolayer of PS-PVP micelles coated on the sidewall and top. ͑d͒ Array of
NCs on the sidewall and top surface.
The inset of Fig. 2͑a͒ shows a 3D schematic diagram of
the fabricated vertical floating gate memory device. The fab-
ricated device structure is the same as a conventional fin-
shaped field electronic transistor except for a wide fin. A
scanning electron microscopy ͑SEM͒ image of the top sur-
face of the device in Fig. 2͑a͒ shows that the NC has a size of
about 9 nm and a density of 2.4ϫ1011/cm2. A comparison of
SEM images confirms that the NCs are formed well even on
the sidewall. As shown in Figs. 2͑a͒ and 2͑b͒, the NCs have
the same size and distribution on the sidewall as on the top.
Figure 3͑a͒ shows the memory characteristics of the ver-
tical floating gate memory device induced from Ϯ11 V for
100 ms pulse of programing and erasing. The device without
NCs shows a negligible VT shift; thus, it confirms that the VT
shift is due solely to the Co NCs. It should be noted that the
single layer of PS-PVP micelles with CoCl2 was covered not
only on the top surface but also on the sidewall of the pattern
because the dip coating of the block copolymer micelles al-
lowed a conformal coating on every surface of the patterned
substrate. The monolayer of micelles coated on the pattern
was treated with oxygen plasma for 10 min, resulting in the
formation of a single-layered array of cobalt oxide NCs on
the top and on the sidewall. During the formation process,
the micellar arrangement was preserved and the organic co-
polymer micelles were removed ͓Fig. 1͑d͔͒. Because pure
metallic Co has a higher charging efficiency than Co oxide,
we conducted hydrogen annealing at 400 °C for 1 h to re-
duce the Co NCs.15,16
For the device fabrication, we used a ͗100͘ p-type
silicon-on-insulator wafer. The wafer has a top silicon layer
of 230 nm with a resistivity of 10–20 ⍀ cm on the 380 nm
thick buried oxide layer. Initially, we deposited a 100 nm
thick hardmask layer of high density plasma ͑HDP͒ oxide to
investigate the effect of the NCs on the sidewall only without
effect of the NCs on the top. The active region was defined
by anisotropic reactive ion etching ͑RIE͒ to obtain a vertical
sidewall profile with the hardmask. To alleviate the surface
of the sidewall damaged by the RIE, we used diluted hydro-
gen fluoride ͑HF͒ for the iterative sacrificial oxidation and
etching. Then, a 4.5 nm layer of tunneling oxide was ther-
mally grown. For the storage node, the Co NCs were synthe-
sized on the tunneling oxide according to the micellar pro-
cesses. A 30 nm thick layer of HfO2, a control oxide, was
then deposited by plasma-enhanced atomic layer deposition
and a 300 nm thick layer of Cr was deposited as a gate
electrode by means of dc sputtering. The Cr gate and the
control oxide were wet etched in sequence. To make a
source/drain region and minimize the lateral straggle of dop-
ants, we used RIE to remove the revealed HDP hardmask
after the control oxide etching. Instead of using a conven-
tional ion implant, we used a plasma immersion of phosphor-
ous ion to produce a shallow and uniform source/drain pro-
file. Additionally, the plasma immersion method has the
advantage of avoiding a high thermal budget, which can melt
metal NCs, for electrical dopant activation and diffusion into
FIG. 3. ͑Color online͒ ͑a͒ The memory characteristics of the fabricated
vertical floating gate memory device with pulses of Ϯ11 V for 100 ms for
the program/erase operations. ͑b͒ The effect of hydrogen annealing on
memory performance. The programing pulse was 11 V for 100 ms.

052106-3
Kim et al.
Appl. Phys. Lett. 93, 052106 ͑2008͒
In summary, we have demonstrated the 3D vertical float-
ing gate memory device with Co NCs synthesized by means
of a reversed micelle structure based on a diblock copolymer.
A uniform NC size and spatial distribution were achieved on
both the sidewall and the top through the use of a monolay-
ered micelle structure formed by means of the dipping
method. In addition, the NC diameter and NC-to-NC space
can be separately controlled by modification of the molecular
weight of each core-shell block. Because metallic Co NCs
have a better charge-trapping efficiency than Co-oxide NCs,
the fabricated device with hydrogen annealing shows a wide
memory window and a prolonged retention time, which pre-
serves more than 60% of the initial charge after ten years.
This research highlights the potential of using a 3D vertical
floating gate memory device with metal NCs through a poly-
meric template in scaled-down devices.
This work was supported by the National Research Pro-
gram for the 0.1-Terabit Nonvolatile Memory Development,
which is sponsored by the Ministry of Knowledge Economy.
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