Selective area growth of high quality InP on Si (001) substrates

Article abstract of DOI:10.1063/1.3491554

In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenches on exactly (001) oriented Si substrates by using a thin Ge buffer layer. Antiphase domain boundaries were avoided by annealing at the Ge surface roughening temperature to create additional atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the corresponding step density control method are illustrated. The elimination of antiphase boundaries from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP layers inside the trenches.

Full text of DOI:10.1063/1.3491554

Selective area growth of high quality InP on Si (001) substrates
G. Wang, M. R. Leys, R. Loo, O. Richard, H. Bender, N. Waldron, G. Brammertz, J. Dekoster, W. Wang, M.
Seefeldt, M. Caymax, and M. M. Heyns
Citation: Applied Physics Letters 97, 121913 (2010); doi: 10.1063/1.3491554
View online: http://dx.doi.org/10.1063/1.3491554
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APPLIED PHYSICS LETTERS 97, 121913 ͑2010͒
Selective area growth of high quality InP on Si „001… substrates
G. Wang,1,2,a͒ M. R. Leys,1 R. Loo,1 O. Richard,1 H. Bender,1 N. Waldron,1 G. Brammertz,1
J. Dekoster,1 W. Wang,1 M. Seefeldt,2 M. Caymax,1 and M. M. Heyns1,2
1IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
2Department of MTM, KULeuven, Kasteelpark Arenberg 44, Box 2450, Leuven B-3001, Belgium
͑Received 6 August 2010; accepted 1 September 2010; published online 22 September 2010͒
In this work, we demonstrate the selective area growth of high quality InP layers in submicron
trenches on exactly ͑001͒ oriented Si substrates by using a thin Ge buffer layer. Antiphase domain
boundaries were avoided by annealing at the Ge surface roughening temperature to create additional
atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the
corresponding step density control method are illustrated. The elimination of antiphase boundaries
from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP
layers inside the trenches. © 2010 American Institute of Physics. ͓doi:10.1063/1.3491554͔
Selective area growth ͑SAG͒ is widely used in fabricat-
ing III–V heterojunction devices and photonic integrated
circuits.1,2 Recently, there has been great interest in integrat-
ing InP and other high mobility materials such as InGaAs on
Si substrates to make high performance complementary
metal oxide semiconductor ͑CMOS͒ devices. One approach
to integrate these materials on Si substrates is SAG in shal-
low trench isolation ͑STI͒ structures.3,4 By utilizing the de-
fect necking effect in submicron trenches, extended defect-
free materials can be obtained.5 SAG also makes it possible
to fabrication Ge p-channel metal oxide semiconductor
͑pMOS͒ devices in the vicinity of III–V n-channel MOS
͑nMOS͒ devices so that high performance CMOS devices
can be realized on a single Si substrate.6 In addition, the
integration of optoelectronic devices on a Si chip will also
likely need SAG of III–V materials on dedicated Si areas.
For III–V compound semiconductor epitaxial layers
grown on Si ͑001͒ or Ge ͑001͒ substrates, the reduced sym-
metry of III–V compounds induces antiphase ͑domain͒
boundaries ͑APBs͒ which cause deep-level defects in the
band gap.7 These APBs are either in ͕111͖ or in ͕110͖ planes.
The APBs in ͕111͖ may get annihilated with increasing layer
thickness8 while the APBs in ͕110͖ will penetrate to the
surface.9 To avoid APBs, miscut Si ͑001͒ or Ge ͑001͒ sub-
strates are commonly used.10,11 Off-oriented Si ͑001͒ or Ge
͑001͒ substrates provide a high density of atomic steps that
form double-B atomic steps at elevated temperatures, pre-
venting APB formation.12 However, miscut substrates induce
additional issues in SAG, such as crystal quality and surface
morphology dependence on trench orientations, resulting in a
significant barrier for their application in CMOS device
fabrication.4,13 In addition, miscut Si ͑001͒ substrates are not
standard in Si CMOS industry. Consequently, it is of great
importance to obtain APB-free III–V layers on exactly ͑001͒
oriented Si substrates.
steps on a Ge surface can be created in a controlled manner
so that the formation of double atomic steps is energetically
favored. Via this mechanism, we have eliminated APBs in
InP grown in Si ͑001͒ STI trenches by using a thin Ge buffer
layer.
Trenches with widths from 0.1 to 0.2 ␮m ͑trench
lengths from 0.5 to 100 ␮m͒ were fabricated on 200 mm Si
͑001͒ wafers by using a typical SiO2 STI patterning scheme
routinely employed in Si-CMOS technologies. The thickness
of STI-SiO2 is 300 nm. After a standard wet clean and an HF
dip, the Si was etched back to a depth of ϳ400 nm by HCl
vapor phase etching at 850 °C and 10 Torr in an ASM-
Epsilon™ 2000 reactor. An in situ H2 bake was used at
850 °C for the removal of the Si native oxide.15 Subse-
quently, a thin ͑ϳ30 nm͒ Ge layer was grown at 450 °C and
atmospheric pressure using GeH4 ͑1% in H2͒ in a H2 carrier
gas. About 10% of the total Si wafer surface was exposed for
the Ge and the subsequent InP deposition.
After the thin Ge layer deposition, the wafers were
cleaved into 50ϫ50 mm2 pieces and loaded into an Aixtron/
Thomas Swan close coupled showerhead metal organic va-
por phase epitaxy reactor. Trimethylindium was used as the
group-III element precursor. For the group V element, tertia-
rybutylarsine ͑TBAs͒ and tertiarybutylphosphine were avail-
able. Before the growth, a pre-epi bake at 740 °C and re-
duced pressure was carried out using TBAs and H2 as a
carrier gas. The purpose of this bake is to remove the Ge
native oxide and to promote double step formation. Follow-
ing this bake, the temperature was ramped down to 420 °C
to grow ϳ30 nm InP seed layer. After the growth of the InP
seed layer, the temperature was ramped to 640 °C for the
bulk InP layer growth. More details of the growth optimiza-
tion can be found in Refs. 4 and 13. The crystalline defects
were characterized with transmission electron microscopy
͑TEM͒.
It has been reported that the atomic steps can be artifi-
cially created on exactly ͑001͒ oriented Si substrates.9 How-
ever, it is well known that, compared to Si, the double steps
on a Ge surface are more stable and easy to form with a
lower thermal budget.14 We will show in this letter, in the
case of SAG, especially in submicron trenches, the atomic
This thin Ge buffer layer is important as Ge double steps
are more stable and can be formed at a much lower tempera-
ture compared to that of Si.16,17 The atomic step creation
mechanism is schematically shown in Fig. 1. A concave sur-
face can be obtained by over etching the Si during the HCl
vapor phase etch step.4,13 Si facets may form in the bottom of
the trenches during the Si etch ͓Fig. 1͑b͔͒. In the wider
trenches ͓Ͼ1 ␮m, depicted on the right side of Fig. 1͑b͔͒,
a͒
Electronic mail: wangga@imec.be.
0003-6951/2010/97͑12͒/121913/3/$30.00
97, 121913-1
© 2010 American Institute of Physics
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121913-2
Wang et al.
Appl. Phys. Lett. 97, 121913 ͑2010͒
STI
(a)
Si (001)
w
STI
(b)
(c)
h
Ge
x
FIG. 2. Bright field cross- section TEM images ͑g͓004͔͒ of InP grown in the
100 nm ͑a͒ and 200 nm ͑b͒ wide STI trenches. ͕111͖ and ͕311͖ Si facets
were obtained after Si etch with HCl vapor. TDs are confined in the bottom
of the trenches.
y
d
l
ing to the double step formation energetics on vicinal Ge
͑001͒ surfaces, to ensure the formation of Ge double steps, a
minimum step density of 0.14 nm−1 ͑equivalent to the step
density on a 2° off-oriented vicinal surface͒ in the vicinity of
ϳ4 nm ͑xϷ4 nm͒ is required.14,16 From Eq. ͑2͒, it is evi-
dent that larger h is needed for wider trenches.
FIG. 1. ͑Color online͒ Schematics of Ge surface step creation in STI
trenches of different widths. ͑a͒ STI trenches are defined on a Si ͑001͒
substrate by standard Si STI processing. ͑b͒ The Si is over etched so that a
concave surface is obtained then a thin Ge layer is deposited followed by
annealing. The zoom-in view of atomic steps on the Ge surface at the center
of a submicron trench is shown in ͑c͒. The parameters associated with
the atomic steps are shown, trench width w, atomic step height, d, terrace
width, l, and the maximum distance from the Ge surface to the reference Si
surface, h.
The concept shown in Fig. 1 is demonstrated experimen-
tally. Figure 2 shows the cross-section TEM images of 100
nm and 200 nm wide trenches after InP growth. Si ͕111͖ and
͕311͖ facets are observed after the Si recess. The sharp edges
could cause voids if InP was directly grown on the faceted Si
surface.3 The thin Ge buffer layer mitigates the sharp edges
and a relatively round surface is obtained. From the slope of
the Ge surface, we can deduce that the step density near the
trench center is significantly larger than 0.14 nm−1 in both
trenches. This rounded Ge surface is crucial for several rea-
sons. First of all, the rounded surface creates a high density
of single atomic steps. Upon annealing at a temperature
above the Ge surface roughening point, single surface steps
migrate and merge into double steps. The formation of
double steps is essential to avoid any APB formation. Sec-
ond, the rounded Ge surface removes facets and the subse-
quent InP growth follows the Ge surface in a step flow
growth mode and thus different crystal orientation can be
avoided. As a result, no void formation occurs. Finally, the
atomic steps on the rounded Ge surface facilitate InP nucle-
ation thereby retarding islanding, which results in an im-
proved InP nucleation layer. The TEM images show no trace
of APBs which means that the artificial Ge surface steps have
transformed into double steps. In addition, all the threading
dislocations ͑TDs͒ are confined at the bottom of the trench.
With the suppression of APBs and by the extended defect
necking effect, a defect-free InP layer is obtained at the top
of the trenches.
the ͑001͒ surface still remains in the center of the trench. In
the next step, a thin Ge layer is grown on the faceted Si
surface. The Ge epitaxial layer follows the starting Si surface
but smoothens the sharp intersection between two adjacent
facets as a result of the different Ge growth rates on the
facets. To create a relatively uniform step density on the Ge
buffer layer, a bake at an elevated temperature is used. At
about 700 °C, the Ge surface roughening temperature, the
step formation energy approaches zero, facilitating surface
step formation.18 As a result of the high temperature anneal,
the Ge surface tends to evolve into a rounded continuous
surface. The atomic step density on the rounded Ge surface
can be estimated analytically by assuming a given surface
profile. In a submicron trench, the surface profile can be
considered elliptical,
x2
y2
h2
+
2
= 1,
͑1͒
w
͑ ͒
2
with w being the trench width and h the maximum distance
from the Ge surface to the reference Si surface ͓see Fig.
1͑c͔͒. x and y are the coordinates of the point of interest. The
surface step density, ␳, is given by ␳=͉y /d͉ with y being
the slope of the surface and d the step height. The surface
Ј
Ј
step density is,
To further confirm the absence of APBs, we performed a
TEM analysis along the length of a 200 nm trench in order
to cover a larger area. Figure 3 shows the cross-section TEM
image of the same trench as in Fig. 2͑b͒. No APBs are
observed in this long trench. Furthermore, a flat and uniform
InP layer grown on the smooth Ge buffer layer along
the complete length of the trench is obtained. This uniform
Ge layer thickness maintains the Ge surface profile and
the surface atomic step density. From Eq. ͑2͒, if the local
y
4hx
Ј
␳ =
=
.
2
͑2͒
ͯ ͯ
ͯ ͯ
2x
w
2
d
dw ͱ1 −
͑ ͒
From Eq. ͑2͒, it can be seen that surface step density depends
on the trench width, w, as well as the maximum distance
between the Ge surface and the Si reference level, h.
In general, the Ge surface step density at the edge of the
trench is much larger than that at the trench center. Accord-
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121913-3
Wang et al.
Appl. Phys. Lett. 97, 121913 ͑2010͒
Logic project ͑Contract No. 214579͒. Dr. Y. Mols and Dr. S.
Degroote are gratefully acknowledged for technical help and
discussion.
InP
TD
STI
Ge
Si
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quality InP in submicron STI trenches on exactly ͑001͒ ori-
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ating atomic steps on a rounded thin Ge buffer layer by an-
nealing the Ge surface at the roughening temperature. An
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The authors would like to acknowledge European Com-
mission for financial support in the frame of the FP7 Dual-
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