Low leakage current structures with subgate in metal-induced unilaterally crystallized silicon thin-film transistors

Article abstract of DOI:10.1149/1.2918899

Low leakage current structures, such as the lightly doped drain and the field-induced drain, employing a subgate were investigated. In order to achieve the self-alignment of a submicrometer level lightly doped drain, the transmittance change in the phase transformation of silicon by a metal-induced lateral crystallization method was employed. Due to an extended thermionic emission domain, more than one order of magnitude improvements in the leakage current at the practical off-state were obtained. Controlling the subgate dielectric resulted in a better on/off current ratio. Simulated results demonstrated that the proposed field-induced drain structure effectively suppressed the electric fields near the drain.

Full text of DOI:10.1149/1.2918899

H536
Journal of The Electrochemical Society, 155 ͑7͒ H536-H539 ͑2008͒
0
013-4651/2008/155͑7͒/H536/4/$23.00 © The Electrochemical Society
Low Leakage Current Structures with Subgate in
Metal-Induced Unilaterally Crystallized Silicon Thin-Film
Transistors
a,z
a
a
b
a
Il-Suk Kang, Sung-Hun Yu, Se-Wan Son, Jeonghun Seo, and Seung-Ki Joo
a
School of Materials Science and Engineering, College of Engineering, Seoul National University,
Seoul 151-742, Korea
b
Neo Poly Incorporated, Seoul National University, Gwanak-gu, Seoul 151-744, Korea
Low leakage current structures, such as the lightly doped drain and the field-induced drain, employing a subgate were investigated.
In order to achieve the self-alignment of a submicrometer level lightly doped drain, the transmittance change in the phase
transformation of silicon by a metal-induced lateral crystallization method was employed. Due to an extended thermionic emission
domain, more than one order of magnitude improvements in the leakage current at the practical off-state were obtained. Control-
ling the subgate dielectric resulted in a better on/off current ratio. Simulated results demonstrated that the proposed field-induced
drain structure effectively suppressed the electric fields near the drain.
©
2008 The Electrochemical Society. ͓DOI: 10.1149/1.2918899͔ All rights reserved.
Manuscript submitted December 28, 2007; revised manuscript received February 27, 2008. Available electronically May 16, 2008.
Polycrystalline silicon ͑poly-Si͒ thin-film transistors ͑TFTs͒ have
been known to have a much higher mobility than amorphous-silicon
a-Si͒ TFTs, which enables high density and high performance dis-
structure because the silicon channel is not damaged by plasma ra-
12
diation during the gate insulator deposition, is seriously limited.
In this study, the representative low leakage current structures,
such as the LDD and the FID, were fabricated employing the sub-
gate. To achieve the self-alignment of the subgate and the formation
of a submicrometer level subgate, a simple process of a successive
etching process using the isotropy of wet etching was employed. In
the LDD, the transmittance change in the phase transformation of
silicon by the MILC method was also employed. The electrical
properties of the proposed TFTs with various effective lengths of the
subgate were investigated. Since the FID region has a two-
dimensional ͑2-D͒ variable, the electrical properties according to
various thicknesses of the subgate dielectric were also investigated.
͑
plays. To use glass substrates for those displays, much attention has
focused on the low-temperature crystallization technology, such as
solid-phase crystallization, excimer laser scanning ͑ELS͒, and
metal-induced lateral crystallization ͑MILC͒. While MILC has many
advantages, such as a low-cost batch process, smoother surface, and
a higher degree of crystalline uniformity, compared to a major tech-
1
nology of ELS, the leakage current of MILC TFTs is reported to be
higher than that of ELS TFTs.
The dominant mechanism of the high leakage current is known
to be the field emission via grain boundary traps due to a high
2,3
electric field in the drain depletion region. Poly-Si TFTs with an
Experimental
offset gate, a lightly doped drain ͑LDD͒, and a field-induced drain
͑
FID͒ structures have been suggested to reduce the electric field near
Figure 1 shows a schematic diagram of the cross section for the
proposed TFTs with a subgate, which is the same as our previous
offset gate structure, thus, most fabrication processes of the LDD
TFTs and the FID TFTs are the same as those of the offset-gated
4
-6
the drain. Among the three structures, the offset-gated TFT exhib-
its the lowest leakage current. However, it does have the lowest
current drive due to the highest series resistance. In our previous
study, the offset-gated MILC TFTs employing a subgate ͑which is
not another gate but another metal layer patterned on the gate͒ were
7
TFTs. ͑Figure 1 also shows the equivalent structures of the LDD
TFTs and the FID TFTs.͒ The only structural differences among the
offset-gated TFTs, the LDD TFTs, and the FID TFTs were: ͑i͒ ma-
terial of the subgate; 500 Å thick sputtered MoW layer for the
offset-gated TFTs and the FID TFTs, and 600 Å thick low-pressure
chemical vapor deposited a-Si layer for the LDD TFTs, ͑ii͒ variable-
ness of the thickness in the subgate dielectric for the FID TFTs ͑for
7
investigated.
The different mechanism of the high leakage current in MILC
TFTs is known to be the highly defective nature of the MILC ma-
terial. That is, Ni-related centers or complexes within the channel
8
make many levels within the bandgap. Though the minimizations
of the concentration of Ni and Ni-silicide ͑NiSi ͒ by a Ni-offset
2
structure and a metal-induced unilateral crystallization ͑MIUC͒
technique improve the leakage current to some degree,
9
,10
respectively,
the leakage current is still high. Another mechanism
is the abrupt drain junction due to the necessity for low activation
annealing temperatures below the warpage temperature of glass sub-
strates where any lateral diffusion is negligible. To relieve an elec-
tric field due to the abrupt drain junction, the LDD structure has
been widely adopted.
The series resistance of the LDD region is not changed with the
gate voltage, so the trade-off between the on-state current and the
leakage current should be considered. So, a poly-Si TFT with the
FID structure, which uses an inversion layer induced by the electric
6
field as a drain, has been suggested.
However, general LDD and FID structures have several deficien-
cies such as the requirements of a high-resolution photolithographic
step for submicrometer level alignment, a chemical-mechanical pol-
11
ishing, etc. Especially, its application to the bottom gate structure,
which has the advantage of a larger on-state current than the top gate
Figure 1. ͑Color online͒ Schematic diagram of ͑a͒ the cross section of the
proposed TFTs with subgate and the equivalent structures of ͑b͒ the LDD
TFTs and ͑c͒ the FID TFTs.
z
E-mail: arock76@naver.com
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Journal of The Electrochemical Society, 155 ͑7͒ H536-H539 ͑2008͒
H537
Figure 2. ͑Color online͒ Schematic cross-
sectional view of key fabrication process
steps for the LDD TFTs with subgate: ͑a͒
successive etching, ͑b͒ annealing for
MIUC, ͑c͒ first IMD after first back-
surface exposure, and ͑d͒ second IMD af-
ter second back-surface exposure.
the offset-gated TFTs and the LDD TFTs, constant nitride layer of
00 Å͒, and ͑iii͒ formation of electrical connection between the
main gate and the subgate for the FID TFTs.
voltage and the radio-frequency power were 15 keV and 150 W,
respectively. When it is exposed from the back surface, the lower
remaining amorphously Si pattern ͑B in Fig. 3͒ is copied on a resist
coating, which shields the silicon channel and the LDD areas from
dopants. After stripping the resist, the dopants were activated during
4
Figure 2 shows the key fabrication process steps for the LDD
TFTs. A 600 Å thick a-Si layer as the subgate was deposited on the
glass substrate ͑Corning 1737͒ by low-pressure chemical vapor
deposition using disilane ͑Si H ͒. A 400 Å thick nitride layer as an
a 550°C anneal for 6 h in H ambient. During this time the whole
2
lower Si layer was crystallized, and hence, at the second back-
surface exposure the only MoW gate pattern was copied on a resist
2
6
insulator was deposited by plasma-enhanced chemical vapor depo-
sition ͑PECVD͒. A 1000 Å thick MoW layer as a main gate elec-
trode was deposited. The main gate patterning and the subgate pat-
terning were performed by only one photolithography with a
conventional mask for defining gates with a width of 10 ␮m and a
length of 10 ␮m ͑W/L = 10/10 ␮m͒. To etch out the edge of the
MoW layer, the substrate was dipped in a MoW etchant. The effec-
tive subgate length ͑LLDD͒ depends on the wet etching period. Then,
the nitride and a-Si layer were etched by reactive ion etching ͑RIE͒.
Then, the edge of the nitride layer was just wet etched again ͓Fig.
2
a͔. Due to this successive etching process at one photolithographic
step, there is no misalignment error between the main gate and the
subgate. Afterward, a 200 Å thick nitride and a 400 Å thick oxide
as gate dielectric layers were prepared by sequential deposition. A
600 Å thick a-Si layer as an active layer was deposited. After de-
fining active islands, a 50 Å thick Ni layer as a catalyst metal for
MIUC was formed by a lift-off process at the whole surface, except
for the dot-filled area “A” in Fig. 3. “a” and “aЈ” denote asymmetric
offset lengths to minimize the concentration of Ni and NiSi in the
2
channel, “b” denotes an offset long enough not to crystallize the
dash-lined area “B” of the lower a-Si layer at the first annealing, and
“
c” is the lateral crystallization length at the first annealing ͑aЈ and
b Ͼ c͒. The upper a-Si layer was crystallized in H2 ambient at
50°C for 6 h, whereas the lower a-Si layer was partially crystal-
5
lized ͑Fig. 2b͒. To define source/drain junctions, the first back-
surface exposure was followed by showering with boron ions in an
ion mass doping ͑IMD͒ system for 4 min ͑Fig. 2c͒. The accelerating
Figure 3. ͑Color online͒ Schematic Ni pattern in the LDD structure.
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Journal of The Electrochemical Society, 155 ͑7͒ H536-H539 ͑2008͒
Table I. Experimental and equivalent thickness of the subgate dielectric films, effective length of the subgate and the main gate, and the ratios
of the maximum on-state current to the minimum leakage current and a leakage current at VGS = 5 V, respectively (Rmin and R5V).
First dielectric films
Second dielectric films
͓
unit: Å͔
͓unit: Å͔
Oxide-equivalent subgate
dielectric/oxide-equivalent
main gate dielectric
͓unit: Å͔
Effective subgate
͑effective main gate͒
͓unit: ␮m͔
Rmin
͓unit:10 ͔
R5V
͓unit: 10 ͔
6
6
Sample
Nitride
Oxide
Nitride
Oxide
Con.
A
B
C
D
—
—
400
400
400
400
400
400
200
200
200
200
200
200
400/400
600/400
600/400
600/400
900/400
1200/400
0 ͑10͒
1 ͑8͒
2 ͑6͒
3 ͑4͒
2 ͑6͒
2 ͑6͒
1.50
1.60
1.85
2.44
2.53
2.46
0.09
0.21
0.82
1.77
2.02
1.94
200
200
200
200
200
100
100
100
400
700
E
coating, and then, when showering with boron ions for 20 s, the
LDD areas were doped ͑Fig. 2d͒. After stripping the resist, another
dopant activation at 550°C for 1 h was performed.
In the FID, after a 500 Å thick sputtered MoW as the subgate
and a PECVD multilayer in order ͑Table I͒ as the first dielectric,
contact holes to connect the subgate to the main gate were formed
is observed that the thermionic emission domain, denoted by L1 in
Fig. 5, where the leakage current is independent of the gate voltage,
appears between VGS = −1.5 and −0.5 V. As LLDD is 2 times longer
͑LLDD = 1.6 ␮m͒, the thermionic emission domain length is 3.5
times longer. This causes the remarkable improvement in a leakage
current at a practical off-state gate voltage. While the minimum
leakage current is around 30 pA, which is about 40% lower than that
of the conventional TFT, a leakage current at VGS = 2 V is much
lower by about one order of magnitude. As LLDD is lengthened to
by RIE. Due to the high dielectric constant of nitride ͑␧ = 7.5͒, a
r
nitride film served as almost a half-thick oxide film ͑␧ = 3.9͒.
r
Results and Discussion
2
.4 ␮m, the thermionic emission domain length is extended up to
Figure 4 shows transmittance measurement data of samples with
the equivalent layer stack to the proposed LDD region before and
after crystallization of the lower Si layer ͓glass/lower Si͑600 Å͒/
nitride͑400ϩ400 Å͒/oxide͑200 Å͒/poly-Si͑600 Å͔͒ from a UV-
visible spectrophotometer ͑HP8452A͒, compared to 600 Å thick
a-Si and poly-Si. It was found that the sample with polycrystalline
lower Si is more transparent to the light of a mercury short arc lamp
VGS = 5 V, but the increasing rate is reduced. This may be because
the current increase caused by the decrease of the effective ͑main͒
gate length cancels out the leakage current reduction caused by the
decrease of the electric field over the LDD region. Worse, the higher
series resistance of the LDD region considerably degrades driving
capability. The field-effect mobility is reduced to less than a third of
that of the conventional TFT.
͑
which provides the g-, h-, and i line of the Hg spectrum only;
Figures 6 and 7 show the IDS-VGS characteristics and distribu-
tions of the on/off current ratios for the proposed FID TFTs, respec-
beneath 350 and above 450 nm the intensity is negligible͒ for litho-
graphy than the sample with amorphous lower Si. Thus, the lower
a-Si layer can be used as an internal mask.
Figure 5 shows the IDS-VGS characteristics of the fabricated LDD
TFTs. The conventional bottom-gated poly-Si TFT without a sub-
gate, indicated by LLDD = 0.0 ␮m, shows the excellent turn-on
2
characteristics with a field-effect mobility of around 60 cm /Vs and
the high minimum leakage current of around 50 pA. The on-state
currents and the minimum leakage current of the device with
LLDD = 0.8 ␮m are similar to those of the conventional TFT. But, it
Figure 4. UV transmittance measurement data of samples. a-Si: glass/a-
Si͑600 Å͒, poly-Si: glass/poly-Si͑600 Å͒, before: glass/a-Si͑600
Å/nitride͑400ϩ400͒/oxide͑200 Å͒/poly-Si͑600 Å͒, after: glass/poly-Si͑600
Å͒/nitride͑400ϩ400 Å͒/oxide͑200 Å͒/poly-Si͑600 Å͒.
Figure 5. ͑Color online͒ The IDS-VGS characteristics of the LDD TFTs.
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Journal of The Electrochemical Society, 155 ͑7͒ H536-H539 ͑2008͒
H539
twice longer ͑sample B͒, the thermionic emission domain length is
four times longer. As LFID is lengthened to 3 ␮m ͑sample C͒, the
thermionic emission domain length is extended up to VGS = 5 V but
the increasing rate is reduced and its field-effect mobility is reduced
to about half of that of the conventional TFT. These can be attrib-
uted to the same reasons as above in the LDD TFT.
To reduce the leakage current at LFID = 2 ␮m without sacrificing
turn-on characteristics, we have vertically controlled TEQ_FID. As
TEQ_FID is thickened 1.5 times ͑sample D͒, the thermionic emission
domain length is the same as that of sample C, whereas R5V of
sample D is twice improved. In sample E with twice TEQ_FID of
sample B or threefold TEQ_MAIN, the thermionic emission domain
length increase is saturated. Because the leakage current is not de-
creased enough to compensate for the on-state current reduction,
R5 V is even deteriorated. Therefore, the maximum R5V is derived
from sample D.
A shift toward a high reverse bias of the transition point, where
the dominant leakage current mechanism shifts from the thermionic
emission ͑L1͒ to the thermionic field emission ͑L2͒, shows that this
proposed structure reduces the electric field. This is consistent with
simulation results. The lateral and the vertical electric fields of the
conventional TFT and sample D at VGS = 5 V, VDS = −3 V were
evaluated by a commercial 2–D simulator for semiconductor device
͑
Silvaco–“Atlas”͒. At the active layer surface over the subgate, the
absolute values of the maximum lateral and the minimum vertical
electric fields of sample D are reduced by 12 and 54%, compared
with those of the conventional TFT, respectively. Therefore, the pro-
posed TFT with a 2 ␮m long subgate and a 900 Å thick subgate
oxide suppressed both the lateral and the vertical electric fields near
the drain and, as a result, had the maximum on/off current ratio.
Figure 6. ͑Color online͒ The IDS-VGS characteristics of the FID TFTs.
tively. Rmin and R5V, the ratios of the maximum on-state current to
the minimum leakage current and a leakage current at VGS = 5 V,
respectively, are compared.
Conclusions
As methods for the low leakage current, we proposed a lightly
doped drain and a field-induced drain structure with a subgate. Us-
ing the transmittance difference between a-Si and poly-Si, we suc-
cessfully fabricated MIUC TFTs with various LDD lengths. Because
of the electric field reduction due to the improvement in the abrupt
drain junction, the proposed TFT with a 1.6 ␮m long LDD showed
a significantly low leakage current with maintaining the turn-on
characteristics. Using a 2-D approach, it was found that the pro-
posed FID TFT with a 2 ␮m long subgate and a 900 Å thick sub-
gate oxide had the maximum on/off current ratio. Simulated results
demonstrated that the proposed TFT suppressed both the lateral and
the vertical electric fields near the drain. Therefore, the proposed
TFTs are promising devices for potential future display applications.
The on-state currents and the minimum leakage current of
sample A, whose effective subgate length ͑LFID͒ is 1 ␮m and whose
oxide-equivalent thickness of the subgate dielectric ͑TEQ_FID͒ is
600 Å, 1.5 times thicker than the oxide-equivalent thickness of the
main gate dielectric ͑TEQ_MAIN, 400 Å͒, are similar to those of the
conventional TFT ͑Con.͒. But, it is observed that the thermionic
emission domain ͑L1͒ appears between VGS = 0 and 1 V. As LFID is
Seoul National University assisted in meeting the publication costs of this
article.
References
1
2
. S. W. Lee and S. K. Joo, IEEE Electron Device Lett., 17, 160 ͑1996͒.
. H. G. Fossum, A. Oritz-Conde, H. Shichijo, and S. K. Banerjee, IEEE Trans.
Electron Devices, ED- 32, 1878 ͑1985͒.
3
4
. K. R. Olasupo and M. K. Hatalis, IEEE Trans. Electron Devices, 43, 1218 ͑1996͒.
. Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, IEEE Electron Device Lett., 25, 194
͑2004͒.
5
. H.-C. Lin, C.-M. Yu, C.-Y. Lin, K.-L. Yeh, T.-Y. Huang, and T.-F. Lei, IEEE
Electron Device Lett., 22, 26 ͑2001͒.
. K. Tanaka, H. Arai, and S. Kohda, IEEE Electron Device Lett., 9, 23 ͑1988͒.
. I.-S. Kang, S.-H. Han, and S.-K. Joo, Electrochem. Solid-State Lett., 10, H296
6
7
͑2007͒.
8
9
. D. Murley, N. Young, M. Trainor, and D. McCulloch, IEEE Trans. Electron De-
vices, 48, 1145 ͑2001͒.
. T. H. Ihn, T. K. Kim, B. I. Lee, and S. K. Joo, Microelectron. Reliab., 39, 53
͑
1999͒.
0. T. K. Kim, T. H. Ihn, B. I. Lee, and S. K. Joo, Jpn. J. Appl. Phys., Part 1, 37, 4244
1998͒.
1. S. Seki, O. Kogure, and B. Tsujiyama, IEEE Electron Device Lett., 8, 434 ͑1987͒.
1
͑
1
Figure 7. Distributions of the on/off current ratios of the FID TFTs ͑20 times
each sample͒.
12. T. Tsujimura, O. Tokuhiro, M. Morooka, T. Miyamoto, K. Miwa, Y. Yoshimura, P.
Andry, and F. Libsch, IEEE Trans. Electron Devices, 49, 576 ͑2002͒.
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