Selective electroless metal deposition for via hole filling in VLSI multilevel interconnection structures

Article abstract of DOI:10.1149/1.2096655

Selective electroless metal deposition process is investigated for via hole filling to provide a planar surface for the fabrication of high density multilevel interconnections. The substrates used in this work consisted of a 1.0 μm thick Al layer covered

Full text of DOI:10.1149/1.2096655

Downloaded on 2015-01-30 to IP 129.81.226.78 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).

Downloaded on 2015-01-30 to IP 129.81.226.78 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).

Downloaded on 2015-01-30 to IP 129.81.226.78 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).

Downloaded on 2015-01-30 to IP 129.81.226.78 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).

Downloaded on 2015-01-30 to IP 129.81.226.78 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).