Appl. Phys. Lett., Vol. 83, No. 13, 29 September 2003
Kim et al.
2649
FIG. 3. C–V characteristics of a Pt/55-Å ZrO /n-type Ge ͑100͒ structure
2
FIG. 4. Leakage current characteristics of a Pt/55-Å ZrO /n-type Ge ͑100͒
stack for both bias polarities. Applied voltage is defined as positive when the
top Pt electrode is positively biased.
2
measured at three different frequencies after forming gas anneal ͑4%
H /N , 400 °C, 30 min͒.
2
2
High-frequency C–V measurements were performed af-
the interfacial dislocation density is expected to improve the
electrical properties of these high-k/Ge gate stacks.
In this letter, the microstructural and electrical character-
ter the forming gas annealing ͑400 °C, 30 min͒ using 7 090
2
m circular capacitor patterns. The capacitance was mea-
sured at various frequencies as a function of gate voltage and
the capacitor was swept from inversion to accumulation and
back to check the amount of hysteresis. As shown in Fig. 3,
a significant amount of frequency dispersion was observed
even after series resistance correction using the two-
istics of ALD-grown ZrO dielectric layers on Ge ͑100͒ sub-
2
strates were reported. Locally epitaxial growth of the ZrO2
films was observed. Failure to obtain high-quality epitaxy
over the entire film is attributed to the very large lattice mis-
match in this system. No amorphous interface layer between
the Ge substrate and crystalline high-k film was observed
through TEM and XPS analyses, indicating that native ger-
manium oxide and suboxides may be unstable under typical
ALD growth conditions or they may be removed by HF-
vapor treatment producing a chemical termination that is
stable during subsequent ALD processing. Although large
hysteresis and frequency dispersion were observed, very low
leakage current densities are promising for the future poten-
tial of epitaxial metal-oxide/Ge gate stacks.
11
frequencies correction method, and a very large hysteresis
Ͼ200 mV͒ was observed across the entire frequency range.
͑
After scanning from inversion to the accumulation condition,
the C–V curve shifted along the positive axis during reverse
scan as a consequence of electron trapping from the n-type
Ge substrate injection. This significant electron trapping ͓3
1
2
12
2
ϫ10 ϳ3.5ϫ10 (/cm )͔ and frequency dispersion are be-
lieved to originate either from the large areal density of in-
terfacial dislocations ͓ϳ7ϫ1012 (/cm )͔ due to the rela-
tively large lattice mismatch or because of a very high
density of interface states due to intrinsic differences in
2
The authors thank Dr. Tamara Radetic of the National
Center for Electron Microscopy at Lawrence Berkeley Na-
tional Laboratory for assistance with TEM. This work was
supported in part by the NSF/SRC Center for Environmen-
tally Benign Semiconductor Manufacturing, award no.
Q423740, DARPA HGI Program, and the Mayfield Stanford
Graduate Fellowship.
bonding corrdination across the chemically-abrupt ZrO /Ge
2
interface. With decreasing measurement frequency, the inver-
sion capacitance was observed to increase significantly. This
may be attributed either to an increase in minority carrier
generation due to the diffusion of impurities from the gate
dielectric into the substrate, or, perhaps, to the interaction of
interface slow states. Although the exact evaluation of the
EOT is impossible due to the significant frequency disper-
sion, an EOT of ϳ13 Å can be extracted from the 10-kHz
C–V data, without quantum-mechanical corrections. For an
1
L. Huang, J. O. Chu, S. A. Goma, C. P. D’Emic, S. J. Koester, D. F.
Canaperi, P. M. Mooney, S. A. Cordes, J. L. Speidel, R. M. Anderson, and
H.-S. P. Wong, IEEE Trans. Electron Devices 49, 1566 ͑2002͒.
C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C.
2
1
2
Saraswat, Tech. Dig. - Int. Electron Devices Meet. 2002, 437 ͑2002͒.
H. Shang, H. Okorn-Schmidt, K. K. Chan, M. Copel, J. A. Ott, P. M.
expected ZrO dielectric constant of ϳ25, the EOT of a
2
3
interfacial layer-free interface structure should be ϳ8 Å. This
matches with C–V measurement result reasonably well
when quantum-mechanical effects are considered.
Kozlowsi, S. E. Steen, H.-S. P. Wong, E. C. Jones, and W. E. Haensch,
Tech. Dig. - Int. Electron Devices Meet. 2002, 441 ͑2002͒.
W. P. Bai, N. Lu, J. Liu, A. Ramirez, D. L. Kwong, D. Wristers, A.
4
Ritenour, L. Lee, and D. Antoniadis, VLSI Tech. Dig. 2003, 121 ͑2003͒.
M. Ritala, K. Kukli, P. I. Raisanen, M. Leskela, T. Sajavaara, and J.
Figure 4 shows the room-temperature leakage current
5
behavior of the ZrO on Ge sample measured at both bias
2
Keinonen, Science 288, 319 ͑2000͒.
K. Nishiguchi and S. Oda, J. Appl. Phys. 92, 1399 ͑2002͒.
M. Copel, M. Gribelyuk, and E. Gusev, Appl. Phys. Lett. 76, 436 ͑2000͒.
I. Barin and O. Knacke, Thermochemical Properties of Inorganic Sub-
6
polarities. Although a large number of interface defects and
low-angle grain boundaries exist in these films, a leakage
current density that is significantly lower than that achieved
7
8
stances ͑Berlin, Springer, 1977͒.
K. Prabhakaran and T. Ogino, Surf. Sci. 325, 263 ͑1995͒.
H. Kim and P. C. McIntyre ͑unpublished͒.
K. J. Yang and C. Hu, IEEE Trans. Electron Devices 66, 1500 ͑1999͒.
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243
1
3
using SiO gate stacks with similar EOT was measured.
9
0
2
1
These excellent leakage current characteristics suggest that
other crystalline high-k metal oxides with closer lattice
match to Ge may be good candidates for epitaxial in
high-k/Ge MOS devices. Moreover, optimization of the
11
12
͑
2001͒.
13
S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, IEEE Electron Device
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP:
interface structure through process changes that may reduce
Lett. 18, 209 ͑1997͒.
1
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