Improvement of memory performance by high temperature annealing of the Al2 O3 blocking layer in a charge-trap type flash memory device

Article abstract of DOI:10.1063/1.3442502

The effect of postdeposition annealing (PDA) of the Al₂ O ₃ blocking layer in a charge-trap type memory device is investigated. Significant improvements are achieved by high temperature PDA at 1100 °C, achieving faster operation speed, good charge retention, and a wide program/erase window. Experimental evidence shows that the underlying mechanism is not the changes in the band gap of the crystallized Al₂ O ₃ but is due to the higher trap density in the Si₃ N ₄ trapping layer at a deeper energy level by the intermixing between Al₂ O₃ and Si₃ N₄. The reduced trapping efficiency of the annealed Al₂ O₃ also helps improve the retention property.

Full text of DOI:10.1063/1.3442502

Improvement of memory performance by high temperature annealing of the Al 2 O 3
blocking layer in a charge-trap type flash memory device
Jong Kyung Park, Youngmin Park, Sung Kyu Lim, Jae Sub Oh, Moon Sig Joo, Kwon Hong, and Byung Jin
Cho
Citation: Applied Physics Letters 96, 222902 (2010); doi: 10.1063/1.3442502
View online: http://dx.doi.org/10.1063/1.3442502
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/96/22?ver=pdfcov
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APPLIED PHYSICS LETTERS 96, 222902 ͑2010͒
Improvement of memory performance by high temperature annealing of the
Al O blocking layer in a charge-trap type flash memory device
2
3
1
1
2
2
3
Jong Kyung Park, Youngmin Park, Sung Kyu Lim, Jae Sub Oh, Moon Sig Joo,
3
1,a͒
Kwon Hong, and Byung Jin Cho
1
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology,
3
73-1 Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea
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3
National Nanofab Center, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea
Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eub, Icheon-si, Gyeonggi-do 467-701,
Republic of Korea
Received 5 February 2010; accepted 8 May 2010; published online 1 June 2010͒
The effect of postdeposition annealing ͑PDA͒ of the Al O blocking layer in a charge-trap type
͑
2
3
memory device is investigated. Significant improvements are achieved by high temperature PDA at
100 °C, achieving faster operation speed, good charge retention, and a wide program/erase
1
window. Experimental evidence shows that the underlying mechanism is not the changes in the band
gap of the crystallized Al O but is due to the higher trap density in the Si N trapping layer at a
2
3
3
4
deeper energy level by the intermixing between Al O and Si N . The reduced trapping efficiency
2
3
3
4
of the annealed Al O also helps improve the retention property. © 2010 American Institute of
2
3
Physics. ͓doi:10.1063/1.3442502͔
Charge-trap type memory device, otherwise known as
tures. For erase characteristic comparison, the devices were
TANOS ͑TiN–Al O –Si N –SiO –Si͒, is one of the most
programmed to ⌬VFB ͑programmed V —initial V ͒ =4 V.
2
3
3
4
2
FB
FB
promising candidates for next generation flash memory tech-
nology. This paper reports that the high-temperature post-
deposition annealing ͑PDA͒ of Al O in a TANOS device
To reach ⌬VFB=4 V programmed state, programming con-
ditions used were 160 ␮s, 250 ␮s, and 100 ␮s at 18 V for
900 °C, 1000 °C, and 1100 °C annealed samples, respec-
tively. Both the P/E speed and the charge retention property
were greatly improved by the high-temperature PDA pro-
cess, and the improvement is most apparent when the PDA
temperature is 1100 °C.
2
3
can significantly improve the memory performance of the
device. It also presents experimental evidence that the domi-
nant mechanism behind such an improvement is not a change
in the band structure of Al O , as expected, but is a change
2
3
To investigate the mechanism of such an improvement
by the high-temperature PDA process, the leakage current
performance was initially checked. The results in Fig. 2͑a͒
do not show a reduction in the leakage current due to the
high-temperature PDA compared to the low temperature
PDA. Therefore, the improved P/E properties after an an-
nealing process at a higher temperature are not likely due to
reduced back tunneling current from the gate electrode.
The band structure of the high-temperature annealed
Al O was also carefully measured by high-resolution x-ray
in the charge trapping property of Al O and silicon nitride.
2
3
After standard gate precleaning, a 4.5 nm thick tunnel
oxide ͑SiO ͒ was thermally grown on a p-type Si substrate,
2
and 6 nm thick Si N was deposited by low-pressure chemi-
3
4
cal vapor deposition to form the charge-trapping layer. For
the blocking oxide, a Al O layer with a thickness of 15 nm
2
3
was deposited on the top of the nitride layer by means of
atomic layer deposition ͑ALD͒ using Eureka 3000 from
Jusung Engineering. The ALD temperature was fixed at
2
3
3
00 °C. Al͑CH ͒ from UP Chemical Co. was used as a
3 3
1
photoelectron spectroscopy ͑XPS͒. The result in the inset of
precursor and ozone was used as an oxidant. After the depo-
sition of the Al O layer, PDA was performed in the tem-
2
3
perature range of 800–1100 °C in a N ambient for 30 s. A
2
150-nm-thick TaN layer was deposited by reactive sputtering
for the gate metal. As plasma etching of crystallized Al O
2
3
can cause plasma-induced damage to the gate stack, the gate
stack etching was stopped after the metal gate etching in
order to exclude the effect of plasma etch damage. Then,
source/drain implantation was done through the dielectric
stacks, and all of the samples underwent a rapid thermal
annealing process at 900 °C for 30 s for activation of the
dopant. The charge trap devices were fabricated with the gate
length of 100 ␮m and width of 100 ␮m.
Figures 1͑a͒ and 1͑b͒ show a comparison of the
program/erase ͑P/E͒ characteristics and charge retention
properties of TANOS devices with different PDA tempera-
FIG. 1. ͑Color online͒ Comparisons of ͑a͒ program and erase characteristics
and ͑b͒ charge retention property of TANOS devices with different PDA
temperatures. For more accurate comparison of retention property, the de-
vices with the equal EOT values were selected for ͑b͒.
a͒Author to whom correspondence should be addressed. Electronic mail:
bjcho@ee.kaist.ac.kr.
0
003-6951/2010/96͑22͒/222902/3/$30.00
96, 222902-1
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© 2010 American Institute of Physics
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222902-2
Park et al.
Appl. Phys. Lett. 96, 222902 ͑2010͒
FIG. 3. ͑Color online͒ ͑a͒ Change in the gate voltage during a constant
current stress test of MIM capacitors with Al O dielectrics annealed at
2
3
FIG. 2. ͑Color online͒ ͑a͒ Comparison of the gate stack leakage currents of
TANOS devices with different PDA temperatures. The inset shows the en-
ergy loss spectrum derived from the O 1s spectrum as measured by XPS.
different temperatures. The inset is the trapping efficiency K as a function of
the PDA temperature, as calculated from the results in ͑a͒. ͑b͒ Si depth
profiles in the gate stacks after high-temperature PDA, as measured by
TOF-SIMS.
͑b͒ Retention property of TANOS devices with different PDA temperatures
measured at 150 and 250 °C. The inset is the flat-band voltage difference
between 150 and 250 °C ͑⌬VFB at 250 °C−⌬VFB at 150 °C͒ as calculated
from the results in ͑b͒.
state can be effectively suppressed by a high-temperature
PDA process, which in turn improves the retention property.
However, the reduced trapping efficiency of Al O alone
Fig. 2͑a͒ shows that there is no meaningful difference in the
extracted energy band gap of the annealed Al O ͑E
2
3
does not by itself sufficiently explain the significant enhance-
ment of the P/E speed and the window shown in Fig. 1͑a͒.
On the other hand, it has been reported that a deeper satu-
rated erase flat-band voltage indicates a higher density of
2
3
G,Al O
2 3
=
7.58 eV, 7.59 eV, and 7.59 eV for samples exposed to
900 °C, 1000 °C, and 1100 °C PDA, respectively͒. This re-
sult implies that the improvement of the P/E property and the
charge retention characteristics cannot be explained simply
in terms of an increase in the conduction band offset of the
crystallized Al O , as claimed in a previous report on Al O
7
accessible charge traps. Moreover, the properties of the
Si3N4 trapping layer/Al2O3 interface have been postulated to
8
play a key role in the erase mechanism. Based on such
2
3
2
3
2
,3
for floating gate type flash memory devices. The high-
temperature retention analysis in Fig. 2͑b͒ also supports the
fact that there is no difference in the extracted band gap. The
higher the temperature becomes, the greater the charge loss
is, as shown in Fig. 2͑b͒. If the difference of the charge loss
is monitored between 150 and 250 °C, it can be considered
to be the pure thermionic emission component of the charge
considerations, it is speculated that intermixing at the inter-
face between the Al O blocking layer and the Si N trap-
2
3
3
4
ping layer may occur during high-temperature PDA, leading
to the diffusion of Al into Si N , which results in yielding
3
4
additional traps at a deeper trapping energy level. Figure 3͑b͒
shows the Si depth profiles of TANOS gate stacks with dif-
ferent PDA temperatures, as measured by time-of-flight
secondary ion mass spectrometry ͑TOF-SIMS͒. Additional Si
ions diffuse out from Si N into the Al O blocking oxide
4
loss. The inset of Fig. 2͑b͒ shows the difference of the
charge loss amount monitored by the flat-band voltage dif-
3
4
2
3
ference between 150 and 250 °C ͑⌬VFB at 250 °C−⌬VFB at
due to the higher PDA temperature, which is evidence of
intermixing between Al O and Si N . If such intermixing
1
50 °C͒ calculated from the results in Fig. 2͑b͒. Surpris-
2
3
3
4
ingly, all of the samples ͑as-deposited, 1000 °C annealed,
and 1100 °C annealed Al O ͒ show an identical curve, prov-
occurs, the diffusion of Al ions toward the Si N trapping
3 4
layer will also take place, resulting in additional traps at a
deeper trapping energy level.
2
3
ing that the difference of the charge loss measured at 150 and
2
50 °C does not depend on the Al O PDA temperature.
The charge loss rate as a function of the PDA tempera-
ture was also investigated. Based on the slope of the plot in
Fig. 4͑a͒ and the charge loss rate, the relative trap density
amount could be extracted as a function of the trap energy
2
3
This is strong evidence that the memory performance im-
provement observed in the Al O sample annealed at a high
temperature is not due to the increased band gap caused by
the crystallization of Al O .
As another possible mechanism, the trapping property of
Al O was investigated. For this test, separate samples with
2
3
9
level, as shown in Fig. 4͑b͒. The result in Fig. 4͑b͒ shows
2
3
that the 1100 °C PDA sample has a higher trap density at a
deeper trap energy level in the Si N trapping layer. There-
2
3
3
4
metal-insulator-metal ͑MIM: TaN–Al O –TaN͒ capacitor
fore, it can be concluded that the additional traps at the
deeper trapping energy level of Si N caused by the inter-
2
3
structure were prepared to study the property of the Al O
2
3
3
4
dielectric itself. Figure 3͑a͒ shows the change in the gate
voltage during a constant current stress test performed on the
MIM capacitors. The amount of trapped charge in Al O as a
mixing between Al O and Si N during the high-
temperature PDA process is the main reason for the im-
proved P/E properties.
2 3 3 4
2
3
function of the injected charge was calculated from the gate
Generally in flash memory devices, the charge retention
characteristics and a wide erase window ͑or a fast erase
5
voltage shift ͑not shown here͒. From the result, the trapping
6
10
efficiency K was extracted. The result of the trapping effi-
speed͒ have a trade-off relationship. The real improvement
ciency K in the inset of Fig. 3͑a͒ clearly shows that the
trapping efficiency is significantly reduced when the PDA
temperature increases. This implies that the trap-assisted tun-
in the charge retention characteristics can only be claimed
when both properties are improved together. The result in
Fig. 4͑c͒ clearly shows the benefit of the high-temperature
neling current through the Al O defect in a programmed
PDA of Al O . In this result, the higher the PDA temperature
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1

222902-3
Park et al.
Appl. Phys. Lett. 96, 222902 ͑2010͒
This work was financially supported by Hynix Semicon-
ductor Inc. The authors would like to thank Jusung Engineer-
ing Co. and UP Chemical Co. for the ALD equipment and
the precursor supports, respectively.
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becomes, the more the charge retention is improved. As ana-
lyzed in Figs. 2–4, the wide erase window and enhanced
retention property upon high-temperature PDA contribute to
the pre-existing intrinsic Si N trap density plus a high trap
8
3
4
density at a deeper trap energy level, possibly due to the
diffusion of Al ions toward Si N and the low trapping effi-
9
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