Selective area growth of InP and defect elimination on Si (001) substrates

Article abstract of DOI:10.1149/1.3571248

We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by using a thin Ge buffer layer. The antiphase domain boundaries in InP layers are suppressed by engineering the local Ge surface profile. The mechanism of atomic step formation and the corresponding method for step density control are presented. We discuss the impact of the surface profile of the Ge buffer layer on the formation of antiphase domain boundaries as well as on InP nucleation. A minimum step density of 0.25 nm^-1 is required to avoid antiphase domain boundaries while a higher step density substantially reduces the stacking faults and twins in the InP nucleation layer. By employing the threading dislocation necking effect and the properly controlled Ge surface profile, high-quality InP layers have been obtained in submicron trenches.

Full text of DOI:10.1149/1.3571248

Journal of The Electrochemical Society, 158 (6) H645-H650 (2011)
0013-4651/2011/158(6)/H645/6/$28.00 The Electrochemical Society
H645
C
V
Selective Area Growth of InP and Defect Elimination on Si (001)
Substrates
a
a
Gang Wang,a,b,z Maarten Leys,a Roger Loo,a, Olivier Richard, Hugo Bender,
*
Guy Brammertz,a Niamh Waldron,a Wei-E Wang,a Johan Dekoster,a Matty Caymax,a,
Marc Seefeldt,b and Marc Heynsa,b
*
aImec, Leuven B-3001, Belgium
bDepartment of Metallurgy and Materials Engineering, Katholieke Universiteit Leuven, Leuven B-3001, Belgium
We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by using a thin Ge buffer layer. The
antiphase domain boundaries in InP layers are suppressed by engineering the local Ge surface profile. The mechanism of atomic
step formation and the corresponding method for step density control are presented. We discuss the impact of the surface profile of
the Ge buffer layer on the formation of antiphase domain boundaries as well as on InP nucleation. A minimum step density of 0.25
nmꢀ1 is required to avoid antiphase domain boundaries while a higher step density substantially reduces the stacking faults and
twins in the InP nucleation layer. By employing the threading dislocation necking effect and the properly controlled Ge surface
profile, high-quality InP layers have been obtained in submicron trenches.
C
V
2011 The Electrochemical Society. [DOI: 10.1149/1.3571248] All rights reserved.
Manuscript submitted January 31, 2011; revised manuscript received March 1, 2011. Published April 7, 2011.
InP has been extensively used in high electron mobility transis-
tors and heterojunction bipolar transistors.1,2 Recently, there has
been arising interest in integrating InP and other high electron-mo-
bility materials such as InGaAs on Si substrates to make high per-
formance complementary metal oxide semiconductor (CMOS) devi-
ces,3,4 One approach to integrate these materials on Si substrates is
selective area growth (SAG) in shallow trench isolation (STI) struc-
tures.5 Despite the large lattice mismatch (8%) between InP and Si
substrates threading dislocations (TDs) can be confined at the bot-
tom of the InP layers by TD necking effect in submicron trenches.5
SAG also allows the fabrication of hetero-channel devices such as
Ge p-type field-effect transistors (pFETs) and III-V nFETs so that
high performance CMOS devices can be realized on a single Si sub-
strate.6 In addition, the integration of III-V materials on Si substrates
is of great importance in the field of optoelectronics and photonics.7
The formation of antiphase domain boundaries (APBs) has been
a long-standing issue for III-V compound semiconductor epitaxial
growth on Si (001) or Ge (001) substrates.8,9 The reduced symmetry
of III-V compounds induces APBs that cause deep traps in the band
gap.10 These APBs are either in {111} or in {110} planes. The
APBs in {111} may get annihilated with increasing layer thick-
ness11 while the APBs in {110} can easily propagate to the sur-
face.12 Miscut Si (001) or Ge (001) substrates are commonly used to
avoid APBs.13,14 Off-oriented substrates provide increased densities
of atomic steps that form double steps at elevated temperatures,
which is essential in preventing APB formation.9 However, miscut
substrates induce additional issues in SAG, such as crystal quality
and surface morphology dependence on trench orientations, result-
ing in a significant barrier for their application in CMOS device fab-
rication.15,16 Furthermore, miscut Si (001) substrates are not stand-
ard in Si CMOS industry. Consequently, it is important to obtain
high-quality III-V layers on nominal Si (001) substrates.
mation of APBs can be avoided. The step density on the Ge buffer
layer surface is optimized by controlling the Ge surface profile.
With the properly controlled Ge buffer layer surface, we can elimi-
nate APBs in InP layers grown in Si (001) STI trenches, especially
in submicron trenches. In addition to the benefit of APB elimination,
a high density of atomic steps on the Ge surface strongly suppresses
the formation of stacking faults (SFs)/twins in the InP layers. By en-
gineering the thin Ge buffer layers, we obtained high-quality InP
layers in submicron STI trenches on Si (001) substrates.
Experimental
Si trenches with nominal widths from 0.1 to 0.2 ꢀm (trench
lengths from 0.5 to 100 ꢀm) were fabricated on 200 mm Si (001)
wafers with standard STI patterning. The trench formation process
gave a tapered sidewall and thus larger trench widths were obtained
at the bottom of the trenches. The trenches were grouped into arrays
to give a filling factor (the fraction of open areas for growth versus
total surface areas) of 0.1. The thickness of STI-SiO2 was 300 nm.
After a standard wet clean and a dip in dilute hydrofluoric acid, the
Si STI wafers were loaded to an ASM-Epsilon 2000 reactor. A bake
in H2 at 850ꢁC was employed to further remove the Si native ox-
ide.20 Then Si was etched back to a depth of ꢂ 400 nm with HCl
vapor at 850ꢁC and 10 Torr. Subsequently, a thin Ge layer was
grown in-situ at 450ꢁC and atmospheric pressure by using GeH4
(1% in H2) and a H2 carrier gas.
After the thin Ge buffer layer growth, the wafers were cleaved
into 50 ꢃ 50 mm2 pieces and were loaded into an Aixtron/Thomas
Swan close-coupled showerhead metalorganic vapor phase epitaxy
(MOVPE) reactor. Trimethylindium (TMIn) was used as the group-
III precursor. Tertiarybutylarsine (TBAs) and tertiarybutylphosphine
(TBP) were employed as the group-V precursors. Before the InP
growth, a pre-epi bake at 720ꢁC and 450 Torr was carried out to
remove the Ge native oxide and to promote the formation of double
steps. TBAs was introduced during the pre-epi bake to form an As-
terminated Ge surface that facilitates the InP nucleation. Following
this bake, the temperature was ramped down to 420ꢁC to grow a 30
nm thick InP nucleation layer. Next, the temperature was ramped to
640ꢁC for the bulk InP layer growth. More details of the growth
conditions were described in Refs. 15 and 16. The crystal defects
and the Ge surface profile were inspected by transmission electron
microscopy (TEM). Low-temperature photoluminescence (PL) mea-
surement was used to characterize the InP SAG layers.
The direct growth of InP on Si (001) substrates proved to be
challenging due to the difficulty of InP nucleation on a Si surface
and a common practice is to use a GaAs intermediate layer.3,17 To
solve the APB issue, atomic steps have been engineered on Si (001)
substrates in the case of GaP growth.12 In contrast to a Si surface,
the double steps on a Ge surface can be formed at a lower tempera-
ture.18 Moreover, the lattice mismatch between InP and Ge is only
half of that between InP and Si, which renders the easier nucleation
of InP on Ge. In addition, Ge growth shows decent growth selectiv-
ity.19 Therefore, it is interesting to investigate the InP growth on a
Ge buffer layer. In this paper, we will show how the atomic steps on
a Ge surface can be created in a controlled manner so that the for-
Mechanism of Ge Surface Step Creation
A Ge buffer layer can be used as a platform for surface step crea-
tion due to its lower surface roughening temperature (> 600ꢁC)
*
Electrochemical Society Active Member.
z E-mail: gang.wang@imec.be

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Journal of The Electrochemical Society, 158 (6) H645-H650 (2011)
compared to that of Si (> 1000ꢁC).4,21,22 Furthermore, Ge double
steps are more stable and can be formed at a much lower tempera-
ture compared to those on Si.21,22 The Ge buffer layer inside a sub-
micron STI trench is expected to form a rounded surface at a tem-
perature near or above the surface roughening point where the step
edge formation energy approaches zero. As a result, the formation
of double steps on a rounded Ge surface can be facilitated by
annealing the Ge buffer layer at a temperature above 600ꢁC.
The step density on the rounded Ge surface can be approximated
analytically by assuming a given surface profile. In a submicron
trench, the surface profile can be considered as an elliptical surface
x2
y2
h2
þ
¼ 1
[1]
ꢀ ꢁ
2
w
2
with w being the trench width and h the maximum distance from the
Ge surface to the reference Si surface (see, Fig. 1c). For a given w, h
determines the Ge surface curvature. x and y are the coordinates of
the point of interest on the surface. The surface step density, qs, can
be obtained from the derivative of the Ge surface profile, qs ¼ |y’/d|,
with d being the step height (0.14 nm) and y’ the slope of the
surface
We propose two approaches to create atomic steps on a Ge buffer
layer surface in STI trenches, namely, on a concave and a convex Ge
surfaces. The mechanism of atomic step creation on a concave Ge
surface is schematically shown in Fig. 1. The concave surface is
obtained by etching Si well below the bottom of STI-SiO2 with HCl
vapor. Si facets such as {111} and {311} are commonly observed.23
In submicron trenches, the (001) surface is encroached by the facets
from both sides. In micron wide trenches (on the right side of Fig.
1b), the (001) surface remains at the center of the trench, which pre-
vents the formation of a high density of atomic steps. As a result,
APBs are expected in wide trenches. After the Si recess, a thin Ge
layer is grown on the faceted Si surfaces. The Ge epitaxial growth fol-
lows the Si surfaces but mitigates the sharp intersection between two
adjacent facets as a result of the lower Ge growth rates on the faceted
surfaces than that on the (001) surface. Although single steps are
expected on the as-grown Ge surface, eventually double steps are
required to effectively avoid APBs in InP. The formation of double
steps requires a single step density (hereafter called step density)
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ ꢂ
0
ꢂ ꢂ
y
4hx
ꢂ ꢂ
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
qs ¼
¼
[2]
ꢂ ꢂ
ꢀ ꢁ
2
d
2x
w
ꢂdw2 1 ꢀ
From Eq. 2, it can be seen that the step density depends on the
trench width, w, and the maximum distance between the Ge surface
and the Si reference surface, h. In general, the Ge surface step den-
sity at the edge of the trench is much larger than that at the trench
center due to the increased surface slope at the edge (see Fig. 1c).
Consequently, there is no concern regarding the double step forma-
tion at the edge of the trench. According to Eq. 2, the lowest step
density on the Ge surface is located at the trench center. The terrace
width corresponding to a step density of 0.25 nmꢀ1 (equivalent to
the step density on a 2ꢁ vicinal surface) is ꢂ 4 nm (l ꢄ 4 nm in Fig.
1d). Consequently, to ensure that the step density approximately 4
nm away from the trench center is larger than 0.25 nmꢀ1, a mini-
mum value of h is required.24–28 It is clear that larger h is needed for
wider trenches.
equal to or larger than 0.25 nmꢀ1 24
To create uniform double steps
.
on the Ge surface, a high temperature bake is needed. For instance, at
720ꢁC, the step formation energy is negligible and the formation of
double step is favored.22 During the high temperature bake, the Ge
surface tends to evolve into a rounded continuous surface as a result
of Ge surface reflow driven by the surface energy minimization.19
This reflow process further smooths the Ge surface and creates a rela-
tively uniform step distribution along the surface.16
To better illustrate the step density distribution from the trench
center to the edge, Eq. 2 is plotted in Fig. 2 for different combina-
tions of h and w. For the same h, the narrowest trench (w ¼ 100 nm)
gives the highest step density. While for a given trench width, a
deeper Ge surface (larger h) results in a higher step density. The
dashed line in Fig. 2 shows the step density with equivalent miscut
angle of 2ꢁ. Consider an ideal symmetrical distribution of atomic
steps at the trench center, to ensure the formation of double steps on
the Ge surface, the central atomic terrace width should be smaller
than 8 nm (twice terrace width on a 2ꢁ vicinal surface).18 If the cen-
tral atomic terrace is significantly larger than this value, there is a
chance for single steps to remain at the center, which may cause
APBs in the InP layer. Figure 2 shows that, for a trench width of
Figure 1. (Color online) Schematics of step formation on a concave thin Ge
buffer layer in STI trenches fabricated on a Si (001) substrate. (a) STI forma-
tion, (b) Si etching with HCl vapor, (c) Ge growth followed by pre-epi bake,
and (d) a zoom-in view of the atomic step configuration on the Ge surface at
the center of the submicron trench (left). l is the terrace width and d is the
step height.
Figure 2. Step density distribution from the trench center toward the edge
for different trench widths, w ¼ 100, 200, and 300 nm. For each trench width,
h ¼ 20 (open) and 50 nm (filled) are plotted for comparison. The dashed line
shows a reference for a miscut angle of 2ꢁ.

Journal of The Electrochemical Society, 158 (6) H645-H650 (2011)
H647
100 nm or below, h can be as small as 20 nm to give sufficient
atomic steps and to avoid APBs formation. In contrast, for a 300 nm
wide trench, much deeper recess (larger h) is required. Therefore, it
is feasible to suppress APBs in narrow trenches on Si (001) sub-
strates by properly engineering the Ge buffer layer surface as will
be shown in the following experimental results.
Based on the same reasoning for the concave surface, it is also
possible to obtain similar step densities on a Ge buffer layer that has
a convex surface. For illustration purpose, a flat Si surface is consid-
ered as shown in Fig. 3. After the Ge growth, a high temperature
anneal is performed to ball up the Ge layer (Fig. 3c). The driving
force for the Ge surface reflow is the surface tension that minimizes
the total surface energy of the Ge layer. At a temperature above
600ꢁC, Ge surface reflow occurs and the shape of the Ge surface
depends on the trench width and on the Ge thickness as schemati-
cally shown in Fig. 3c. Similarly, the step density as a function of
the trench width and the distance from the trench center to edge can
be calculated using Eq. 2.
The advantage of these two approaches is that the Ge surface
steps can be created locally in submicron trenches. Since the TD
necking effect has a strict constraint on the aspect ratio (> 2) of
trenches,5 the width of the STI trenches must be narrower than
100–150 nm for a typical STI depth of 300 nm in order to obtain
TD-free InP layers in the top region of the trenches. From Fig. 2,
one can see that a curved Ge surface (h < 50 nm) provides sufficient
step densities to form double steps in narrow trenches (w < 200 nm).
Therefore, the combination of Ge surface engineering and the TD
necking effect gives excellent chance to obtain high-quality InP
layers in submicron STI trenches on Si (001) substrates.
Figure 4. (Color online) Bright-field cross-sectional TEM (g ¼ [004])
images of InP in 100 nm (a) and 200 nm (b) wide trenches. Both trenches
have a concave Ge surface. The h in (a) and (b) is 80 and 120 nm,
respectively.
Figs. 4a and 4b, respectively. Both trenches are formed to obtain a
depth of 100–150 nm below the Si reference surface. {111} and
{311} facets are observed on the Si surfaces and the (001) surface is
absent. After the thin Ge layer growth and the bake prior to InP
growth, the {111} and {311} facets are replaced with a rounded or
high-index Ge surface. In both trenches, the maximum distance
from the Ge surface to the Si reference surface, h (¼ 80–20 nm), is
fairly large. This ensures a high step density near the trench center
(0.91 and 0.43 nmꢀ1, respectively) and thus the formation of double
steps is favored during the pre-epi bake. As a result, APB is sup-
pressed in the InP layers. In addition to the formation of double
steps in the over-etched trenches, there is another advantage associ-
ated with the concave Ge surfaces, namely, an increased aspect ratio
that enhances the TD necking effect. The effective TD confinement
in Fig. 4a is a combined effect of both TD redirection (indicated by
the arrow) by the {111} facets and TD necking by the STI side-
walls.16 This TD bending behavior in InP is the same as what has
been observed in Ge layers selectively grown in trenches.29 In addi-
tion, SFs/twins are not observed in the lower part of InP in these
trenches, indicating improved InP nucleation on the Ge surface.15,16
The InP nucleation has been facilitated on the stepped Ge surface,
especially by the high step density as will be further elaborated in
the following sections.
InP Growth on a Concave Ge Surface
To demonstrate the elimination of APBs in submicron trenches,
we first investigated InP growth on the concave Ge surfaces shown
in Fig. 4. The nominal trench widths are 100 and 200 nm for
The defect statistics of the top region of trenches by cross-sec-
tional TEM analysis is given in Table I. In the 100 nm wide
trenches, TDs are absent in the top region of the trenches but some
SFs are present. The TDs are confined at the bottom of trenches due
to the large aspect ratio (ꢂ 3). In addition to the TD necking effect,
the TD bending by the {111} facets plays an important role, see Fig.
4a. In the 200 nm wide trenches, only TDs are present in the top 50
nm region of the trenches while no SFs are found. The presence of
TDs is caused by the reduced trench aspect ratio (1.5). The TD
bending behavior in Fig. 4b is less pronounced because the TDs
propagate along the [001] direction until the InP layer grows above
the Si reference surface, implying that there are not {111} facets at
the early stage of InP growth. Upon continued growth, the formation
Table I. Summary of defects present in the top 50 nm region of
trenches observed in cross-sectional TEM images taken perpen-
dicular to the trenches.
Trench
width
Filling
factor
STI
taper angle
Aspect
ratio
Defects/
Samples
SFs
TDs
Figure 3. (Color online) Schematic illustration of surface steps on a convex
Ge surface inside STI trenches. (a) Trench formation, (b) Ge growth, (c) pre-
epi bake, (d) zoom-in view of the atomic step configuration on the Ge surface
at the trench center of the submicron trench (left).
100
200
0.1
0.1
6–8ꢁ
6–8ꢁ
3
1.5
3
0
0
1
3/5
1/5

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Journal of The Electrochemical Society, 158 (6) H645-H650 (2011)
of {111} facts starts to bend the TDs. As a result, the TD bending
effect in the wide trench is retarded compared to the narrow
trenches. Although Fig. 4 shows nearly the same STI tapering angle
for both trenches, the 100 nm wide STI trenches are worm-like
when inspected from top with scanning electron microscope (SEM).
The variation in local STI sidewall tapering angles contributes to
the SF/twin formation.15 In contrast, the 200 nm wide trenches are
nearly straight and the STI sidewall tapering angle is uniform. De-
spite the different defect distribution between the two trenches,
APBs are not observed in both cases.
To summarize, it has been experimentally confirmed by TEM
analysis that the effective elimination of APBs requires a minimum
step density of 0.25 nmꢀ1. This finding agrees with the previous
study on vicinal Si (001) substrates.30 The concave Ge surface with
minimum step density higher than the critical value proved to be
beneficial in both APB elimination and TD confinement.
InP SF/twin Formation on the Ge Surfaces
Although the formation of growth-induced defects (SFs/twins) of
InP in STI trenches has been shown to be dependent on the growth
rate and the steric hindrance effect at the STI sidewalls in the previ-
ous study,15 the dissociation of TDs into SFs can hardly be avoided
due to the low SF energy of InP.31 This turns out to be a great chal-
lenge of obtaining defect-free InP layers. In addition, a rather large
number of the SFs/twins originate from the InP seed layer. As InP
nucleation on a flat Ge surface proceeds with Stranski–Krastanov
(SK) growth mode, SFs/twins occur when two islands merge.32
These planar defects are located in {111} planes. Since there are
four equivalent {111} planes that are available for SF/twin propaga-
tion during the growth, the chance for SFs/twins to penetrate
through the InP layer is high. Consequently, it is indispensible to
suppressing SFs/twins during the growth of the InP seed layer. One
solution is to modify the InP nucleation in a way that islanding is
suppressed to the greatest extent. It is well known that the layer-by-
layer growth of a heavily lattice-mismatched epitaxial layer is ener-
getically unfavorable.33 Therefore, the growth of InP on a flat Ge
surface leads to island formation.16 However, islanding can be miti-
gated by step-flow growth mode on a stepped surface. On the
stepped Ge surface, especially in the presence of a high step density,
InP nucleation is facilitated by the step-flow growth mode given a
low growth rate. Because the InP seed layer is grown at 420ꢁC a
low In flux to the surface must be used. At this temperature, the sur-
face mobility of In atoms is reduced and thus a longer time is
needed for the In atoms to migrate to the step edges. If the atomic
terrace width is significantly smaller than the In adatom surface dif-
fusion length, there is excellent chance for the adatoms to migrate to
step edges and to get incorporated into the lattice. As a result, a
small terrace width is essential in maintaining step-flow growth.34
The step-flow growth mode can significantly suppress the island for-
mation35,36 and thus reduce the density of SFs/twins that originate
in the InP nucleation layer.
To further study the effective elimination of APBs by the artifi-
cially created atomic steps on the Ge surfaces, we changed the Ge
surface curvature by using different Ge buffer layer thicknesses.
The cross-sectional TEM images of 200 nm wide trenches with 50
nm and 100 nm thick Ge buffer layers are shown in Fig. 5. Both
samples have received identical Si recess and InP growth condi-
tions. The Ge surface profiles in 5a and 5b give h ¼ 120 and 70 nm,
respectively. From Eq. 2, the step densities 4 nm away from the
trench center are 0.43 and 0.20 nmꢀ1, respectively. Since the mini-
mum step density required for double step formation and for APB
elimination is 0.25 nmꢀ1, it is expected that APBs can be eliminated
in Fig. 5a but not in Fig. 5b. This prediction is consistent with the
observation in Figs. 5c and 5d. There is no APB in the 5 ꢀm long
trench in Fig. 5c, substantiating that APBs are successfully elimi-
nated. The horizontal line in the middle of the InP layer is caused by
the sample thickness contrast. When the InP grows above the STI
surface, the lateral growth (see Fig. 4b) changes the InP thickness.
Note the effective TD necking effect in Fig. 5c. In contrast, several
APBs are found in Fig. 5d. The APBs penetrate though the layer
and propagate to the InP layer surface. Additionally, the presence of
APBs in Fig. 5d disturbs the InP crystal growth and thus more TDs
are found in the upper part of the InP layer bounded by two APBs.
This implies that the interaction of APBs with TDs can change the
propagation of TDs. In addition, the APBs in Fig. 5d induce dips at
the InP surface due to thermal etching effect.16 This phenomenon
can be used to qualitatively evaluate the presence of APBs in InP
with SEM.
The influence of the surface step density on the formation of
SFs/twins was studied on the Si (001) substrates with different Ge
surface profile as shown in Figs. 5a and 5b. Higher-magnification
cross-sectional TEM images of these two samples are shown in
Fig. 6. In Fig. 6a, the Ge surface step density near the trench center
has been extracted to be 0.43 nmꢀ1. The Ge surface step density
increases from the trench center to the edge. Consequently, on this
highly stepped Ge surface, the InP nucleation is expected to proceed
Figure 5. Bright-field cross-sectional TEM images (g ¼ [004]) of 200 nm
wide trenches with different Ge buffer layer thickness, 50 nm (a) and 100 nm
(b). The corresponding cross-sectional TEM images along the trench length
direction are shown in (c) and (d).
Figure 6. Bright-field cross-sectional TEM images (g ¼ [004]) of InP
layers grown on concave Ge surfaces with 50 nm (a) and 100 nm (b)
thick Ge buffer layers. These are the zoom-in images of Figs. 5c and 5d,
respectively.

Journal of The Electrochemical Society, 158 (6) H645-H650 (2011)
H649
wide STI trenches for APB elimination in the subsequent InP layer.
As a result, APBs are present (see Fig. 7b). A striking feature of
Fig. 7 is the much higher density of twins compared to Figs. 5a and
5c, similar to Figs. 5d and 6b where the step density is not sufficient
to promote double step formation and step-flow growth. The pres-
ence of a high density of SFs/twins degrades the InP layer quality
substantially. From the above discussion, it can be concluded that
the Ge surface profile plays a critical role in suppressing both APBs
and SFs/twins in the InP layers.
PL Characterization
Although TEM is a powerful technique for characterizing APBs
and other extended defects, the limited TEM sampling area lacks
statistics in evaluating the InP quality. In addition, optically or elec-
trically active point defects cannot be identified with TEM. There-
fore, PL measurement was performed to give complementary quali-
tative information about the quality of InP layers grown on the
optimized Ge buffer layers.
Figure 7. Bright field cross-sectional TEM images (g ¼ [004]) of InP layers
grown on a convex Ge surface in 150 nm wide trenches, (a) perpendicular to
the trench and (b) along the trench length direction.
The PL spectrum of the InP SAG sample in Fig. 4b is plotted in
Fig. 8. For the purpose of comparison, a 50 mm Fe-doped semi-
insulating bulk InP substrate (InP Ref.) was measured at the same
conditions. The reference InP peak at 1.408 eV is the characteristic
of band-to-band recombination and the side peak at 1.371 eV is
related to the deep level defects.37 The InP peak of SAG sample
shifts to 1.404 eV, implying that the electron-hole recombination
occurs at shallow donor centers. The donor characteristics of the InP
SAG sample is attributed to the background incorporation of either
carbon or Ge.38 The carbon background comes from the metalor-
ganic precursors, which is a well known issue.39 Using a Ge buffer
layer may also result in n-type doping by Ge up-diffusion into the
InP layer although this needs to be further investigated. The InP
SAG sample shows enhanced PL response but also a broadened
peak with full width at half maximum (FWHM) of 21 meV, larger
than the FWHM of the InP reference sample, 10 meV. The peak
broadening is ascribed to the n-type background doping which can
with step-flow mode. As a result, InP islanding is suppressed during
the seed layer growth. It can be seen in Fig. 6a, there are no SFs/
twins in the lower part of the InP layer, especially at the InP/Ge
interface. SFs/twins are occasionally found in the upper part of the
layer due to the TD dissociation that is unavoidable. It has to be
pointed out that the density of SFs/twins is very low in this sample
and they are exclusively found in the upper part of the layer. In con-
trast, Fig. 6b shows a much higher density of SFs/twins in the InP
layer. These SFs/twins consistently start from the InP/Ge interface.
The presence of the high density of SFs/twins indicates that the InP
seed layer growth proceeds via SK growth mode, leading to a high
density of islands. Clearly, for this sample, the Ge surface step den-
sity is not high enough to promote step-flow growth, particularly at
a low temperature, like 420ꢁC.
be estimated from the FWHM to be ꢂ 1 ꢃ 1017 cm
.
ꢀ3 37 Despite the
InP Growth on Convex Ge Surfaces
broadened peak, the strong PL response of the InP SAG layer is in
agreement with the high crystal quality observed by the TEM
images shown in Figs. 5a and 5c.
To further study the impact of the Ge surface profile on the InP
growth and the defect formation, we carried out InP growth on con-
vex Ge surfaces that were obtained by growing a relatively thick Ge
layer followed by a pre-epi bake. The Si recess time is reduced and
only {311} facets are present. With similar growth conditions as
used for the InP layer shown in Fig. 4, InP was grown on the convex
Ge surface and the cross-sectional TEM images are shown in Fig. 7.
The convex Ge surface gives h ¼ 10 nm (Fig. 7a), which is unfortu-
nately not sufficient to provide enough step density in this 150 nm
Conclusions
We have demonstrated the SAG of high-quality InP layers in
submicron STI trenches on nominal Si (001) substrates. The APBs
are suppressed by a sufficiently high density of steps on the thin Ge
buffer layer baked at 720ꢁC. The surface step density is determined
by both the trench width and curvature of the Ge surface profile.
The Ge surface step density can be controlled by changing the Si
recess profile and the Ge buffer layer thickness. A critical surface
step density larger than 0.25 nmꢀ1, or an equivalent surface mis-ori-
entation > 2ꢁ must be maintained in order to eliminate APBs
successfully.
We also found that SFs/twins were substantially suppressed in
the InP nucleation layer on a concave Ge surface with a high step
density, which is attributed to the step-flow growth mode during the
InP nucleation. Since SFs/twins can penetrate to the top region of
the trenches, it is of great importance to strictly suppress the forma-
tion of SFs/twins in the InP nucleation layer. Both the TEM analysis
and PL measurements show that a high density of Ge surface steps
give high-quality InP layers.
The Ge surface engineering method avoids APB formation in the
SAG of III-V epitaxial layers on nominal (001) elementary semicon-
ductor substrates. The elimination of APBs together with the TD
necking effect, yields high-quality InP layers in submicron STI
trenches, which provides a platform for the fabrication of III-V
channel-based devices on Si (001) substrates. This work also gives
insights into the SAG of other III-V zinc blende compound semicon-
ductor epitaxial growth on Si (001) substrates.
Figure 8. PL spectra (77 K) of semi-insulating InP substrate (InP ref.) and
the InP SAG layer in 200 nm wide STI trenches (Fig. 4b). The FWHMs of
the InP ref peak are 10 and 21 meV for the InP reference and the SAG sam-
ple, respectively.

H650
Journal of The Electrochemical Society, 158 (6) H645-H650 (2011)
16. G. Wang, M. Leys, N. D. Nguyen, R. Loo, G. Brammertz, O. Richard, H.
Bender, J. Dekoster, M. Meuris, M. M. Heyns, et al., J. Electrochem. Soc.,
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Acknowledgment
The authors acknowledge European Commission for financial
support in the frame of the FP7 DualLogic project (contract no.
214579). Dr. Marc Meuris, Dr. Y. Mols, and Dr. S. Degroote are
gratefully acknowledged for discussion and technical help.
Imec assisted in meeting the publication costs of this article.
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